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| author | Richard Earnshaw <rearnsha@arm.com> | 2002-03-25 22:22:35 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2002-03-25 22:22:35 +0000 |
| commit | f2356393602878fcb3aca3a3b7661bba030f2fbf (patch) | |
| tree | 1fb76096c2c1aca02debe92d063af56b2965f7a4 /gcc/config/arm | |
| parent | f695acf69c0672e7b70075fb6f8c98119f332d9a (diff) | |
| download | gcc-f2356393602878fcb3aca3a3b7661bba030f2fbf.zip gcc-f2356393602878fcb3aca3a3b7661bba030f2fbf.tar.gz gcc-f2356393602878fcb3aca3a3b7661bba030f2fbf.tar.bz2 | |
re PR target/2623 ([ARM/2.95] Wrong code when accessing unsigned short in a structure.)
PR target/2623
* arm.md (loadhi_preinc, loadhi_predec, loadhi_shiftpreinc)
(loadhi_shiftpredec, loadhi-with-writeback peephole): Don't use
these patterns on arm_archv4.
From-SVN: r51345
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/arm.md | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 7d73cbd..77be4f3 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8280,6 +8280,7 @@ "TARGET_ARM && !BYTES_BIG_ENDIAN && !TARGET_MMU_TRAPS + && !arm_arch4 && REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG @@ -8298,6 +8299,7 @@ "TARGET_ARM && !BYTES_BIG_ENDIAN && !TARGET_MMU_TRAPS + && !arm_arch4 && REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG @@ -8462,6 +8464,7 @@ "TARGET_ARM && !BYTES_BIG_ENDIAN && !TARGET_MMU_TRAPS + && !arm_arch4 && REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" @@ -8482,6 +8485,7 @@ "TARGET_ARM && !BYTES_BIG_ENDIAN && !TARGET_MMU_TRAPS + && !arm_arch4 && REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" @@ -8545,6 +8549,7 @@ "TARGET_ARM && !BYTES_BIG_ENDIAN && !TARGET_MMU_TRAPS + && !arm_arch4 && REGNO (operands[0]) != REGNO(operands[1]) && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))" |