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| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2009-08-20 08:09:29 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2009-08-20 08:09:29 +0000 |
| commit | a552b644fb1f7fe9eb3fd637839007669edd221c (patch) | |
| tree | bd85b09ef5c6933e665835ee19e44cea0afdcc28 /gcc/config/arm | |
| parent | 2fd74bffecf5255a07b42e935c8e44cb55414841 (diff) | |
| download | gcc-a552b644fb1f7fe9eb3fd637839007669edd221c.zip gcc-a552b644fb1f7fe9eb3fd637839007669edd221c.tar.gz gcc-a552b644fb1f7fe9eb3fd637839007669edd221c.tar.bz2 | |
Fix twolf ICE for ARM
2009-08-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <richard.earnshaw@arm.com>
* config/arm/arm.c (arm_emit_movpair): Handle CONST_INT.
* config/arm/arm.md (*arm_movtas_ze): New pattern for
movt.
2009-08-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <richard.earnshaw@arm.com>
* testsuite/gcc.target/arm/20090811-1.c: New test.
Co-Authored-By: Richard Earnshaw <rearnsha@arm.com>
From-SVN: r150953
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/arm.c | 25 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 11 |
2 files changed, 28 insertions, 8 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 993d121..e7e6bee 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -11558,14 +11558,23 @@ output_mov_long_double_arm_from_arm (rtx *operands) return ""; } - -/* Emit a MOVW/MOVT pair. */ -void arm_emit_movpair (rtx dest, rtx src) -{ - emit_set_insn (dest, gen_rtx_HIGH (SImode, src)); - emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src)); -} - +void +arm_emit_movpair (rtx dest, rtx src) + { + /* If the src is an immediate, simplify it. */ + if (CONST_INT_P (src)) + { + HOST_WIDE_INT val = INTVAL (src); + emit_set_insn (dest, GEN_INT (val & 0x0000ffff)); + if ((val >> 16) & 0x0000ffff) + emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode, dest, GEN_INT (16), + GEN_INT (16)), + GEN_INT ((val >> 16) & 0x0000ffff)); + return; + } + emit_set_insn (dest, gen_rtx_HIGH (SImode, src)); + emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src)); + } /* Output a move from arm registers to an fpa registers. OPERANDS[0] is an fpa register. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5d12f90..09a1b08 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11050,6 +11050,17 @@ [(set_attr "conds" "clob")] ) +(define_insn "*arm_movtas_ze" + [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") + (const_int 16) + (const_int 16)) + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_32BIT" + "movt%?\t%0, %c1" + [(set_attr "predicable" "yes") + (set_attr "length" "4")] +) + ;; Load the FPA co-processor patterns (include "fpa.md") ;; Load the Maverick co-processor patterns |