arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

This patch adds an attribute to the mve md patterns to be able to identify
predicable MVE instructions and what their predicated and unpredicated variants
are.  This attribute is used to encode the icode of the unpredicated variant of
an instruction in its predicated variant.

This will make it possible for us to transform VPT-predicated insns in
the insn chain into their unpredicated equivalents when transforming the loop
into a MVE Tail-Predicated Low Overhead Loop. For example:
`mve_vldrbq_z_<supf><mode> -> mve_vldrbq_<supf><mode>`.

gcc/ChangeLog:

	* config/arm/arm.md (mve_unpredicated_insn): New attribute.
	* config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
	(MVE_VPT_UNPREDICATED_INSN_P): Likewise.
	(MVE_VPT_PREDICABLE_INSN_P): Likewise.
	* config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
	* config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
	(arm_vcx1q<a>v16qi): Likewise.
	(arm_vcx1qav16qi): Likewise.
	(arm_vcx1qv16qi): Likewise.
	(arm_vcx2q<a>_p_v16qi): Likewise.
	(arm_vcx2q<a>v16qi): Likewise.
	(arm_vcx2qav16qi): Likewise.
	(arm_vcx2qv16qi): Likewise.
	(arm_vcx3q<a>_p_v16qi): Likewise.
	(arm_vcx3q<a>v16qi): Likewise.
	(arm_vcx3qav16qi): Likewise.
	(arm_vcx3qv16qi): Likewise.
	(@mve_<mve_insn>q_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_int_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_<supf>v4si): Likewise.
	(@mve_<mve_insn>q_n_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_r_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_f<mode>): Likewise.
	(@mve_<mve_insn>q_m_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_m_f<mode>): Likewise.
	(@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_p_<supf>v4si): Likewise.
	(@mve_<mve_insn>q_p_<supf><mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
	(mve_v<absneg_str>q_f<mode>): Likewise.
	(mve_<mve_addsubmul>q<mode>): Likewise.
	(mve_<mve_addsubmul>q_f<mode>): Likewise.
	(mve_vadciq_<supf>v4si): Likewise.
	(mve_vadciq_m_<supf>v4si): Likewise.
	(mve_vadcq_<supf>v4si): Likewise.
	(mve_vadcq_m_<supf>v4si): Likewise.
	(mve_vandq_<supf><mode>): Likewise.
	(mve_vandq_f<mode>): Likewise.
	(mve_vandq_m_<supf><mode>): Likewise.
	(mve_vandq_m_f<mode>): Likewise.
	(mve_vandq_s<mode>): Likewise.
	(mve_vandq_u<mode>): Likewise.
	(mve_vbicq_<supf><mode>): Likewise.
	(mve_vbicq_f<mode>): Likewise.
	(mve_vbicq_m_<supf><mode>): Likewise.
	(mve_vbicq_m_f<mode>): Likewise.
	(mve_vbicq_m_n_<supf><mode>): Likewise.
	(mve_vbicq_n_<supf><mode>): Likewise.
	(mve_vbicq_s<mode>): Likewise.
	(mve_vbicq_u<mode>): Likewise.
	(@mve_vclzq_s<mode>): Likewise.
	(mve_vclzq_u<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
	(mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
	(mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
	(mve_vcvtaq_<supf><mode>): Likewise.
	(mve_vcvtaq_m_<supf><mode>): Likewise.
	(mve_vcvtbq_f16_f32v8hf): Likewise.
	(mve_vcvtbq_f32_f16v4sf): Likewise.
	(mve_vcvtbq_m_f16_f32v8hf): Likewise.
	(mve_vcvtbq_m_f32_f16v4sf): Likewise.
	(mve_vcvtmq_<supf><mode>): Likewise.
	(mve_vcvtmq_m_<supf><mode>): Likewise.
	(mve_vcvtnq_<supf><mode>): Likewise.
	(mve_vcvtnq_m_<supf><mode>): Likewise.
	(mve_vcvtpq_<supf><mode>): Likewise.
	(mve_vcvtpq_m_<supf><mode>): Likewise.
	(mve_vcvtq_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_to_f_<supf><mode>): Likewise.
	(mve_vcvtq_n_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_n_to_f_<supf><mode>): Likewise.
	(mve_vcvtq_to_f_<supf><mode>): Likewise.
	(mve_vcvttq_f16_f32v8hf): Likewise.
	(mve_vcvttq_f32_f16v4sf): Likewise.
	(mve_vcvttq_m_f16_f32v8hf): Likewise.
	(mve_vcvttq_m_f32_f16v4sf): Likewise.
	(mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
	(mve_vdwdupq_wb_u<mode>_insn): Likewise.
	(mve_veorq_s><mode>): Likewise.
	(mve_veorq_u><mode>): Likewise.
	(mve_veorq_f<mode>): Likewise.
	(mve_vidupq_m_wb_u<mode>_insn): Likewise.
	(mve_vidupq_u<mode>_insn): Likewise.
	(mve_viwdupq_m_wb_u<mode>_insn): Likewise.
	(mve_viwdupq_wb_u<mode>_insn): Likewise.
	(mve_vldrbq_<supf><mode>): Likewise.
	(mve_vldrbq_gather_offset_<supf><mode>): Likewise.
	(mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
	(mve_vldrbq_z_<supf><mode>): Likewise.
	(mve_vldrdq_gather_base_<supf>v2di): Likewise.
	(mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
	(mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
	(mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
	(mve_vldrdq_gather_offset_<supf>v2di): Likewise.
	(mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
	(mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
	(mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
	(mve_vldrhq_<supf><mode>): Likewise.
	(mve_vldrhq_fv8hf): Likewise.
	(mve_vldrhq_gather_offset_<supf><mode>): Likewise.
	(mve_vldrhq_gather_offset_fv8hf): Likewise.
	(mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
	(mve_vldrhq_gather_offset_z_fv8hf): Likewise.
	(mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
	(mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
	(mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
	(mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
	(mve_vldrhq_z_<supf><mode>): Likewise.
	(mve_vldrhq_z_fv8hf): Likewise.
	(mve_vldrwq_<supf>v4si): Likewise.
	(mve_vldrwq_fv4sf): Likewise.
	(mve_vldrwq_gather_base_<supf>v4si): Likewise.
	(mve_vldrwq_gather_base_fv4sf): Likewise.
	(mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
	(mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
	(mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
	(mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
	(mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
	(mve_vldrwq_gather_base_z_fv4sf): Likewise.
	(mve_vldrwq_gather_offset_<supf>v4si): Likewise.
	(mve_vldrwq_gather_offset_fv4sf): Likewise.
	(mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
	(mve_vldrwq_gather_offset_z_fv4sf): Likewise.
	(mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
	(mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
	(mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
	(mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
	(mve_vldrwq_z_<supf>v4si): Likewise.
	(mve_vldrwq_z_fv4sf): Likewise.
	(mve_vmvnq_s<mode>): Likewise.
	(mve_vmvnq_u<mode>): Likewise.
	(mve_vornq_<supf><mode>): Likewise.
	(mve_vornq_f<mode>): Likewise.
	(mve_vornq_m_<supf><mode>): Likewise.
	(mve_vornq_m_f<mode>): Likewise.
	(mve_vornq_s<mode>): Likewise.
	(mve_vornq_u<mode>): Likewise.
	(mve_vorrq_<supf><mode>): Likewise.
	(mve_vorrq_f<mode>): Likewise.
	(mve_vorrq_m_<supf><mode>): Likewise.
	(mve_vorrq_m_f<mode>): Likewise.
	(mve_vorrq_m_n_<supf><mode>): Likewise.
	(mve_vorrq_n_<supf><mode>): Likewise.
	(mve_vorrq_s<mode>): Likewise.
	(mve_vorrq_s<mode>): Likewise.
	(mve_vsbciq_<supf>v4si): Likewise.
	(mve_vsbciq_m_<supf>v4si): Likewise.
	(mve_vsbcq_<supf>v4si): Likewise.
	(mve_vsbcq_m_<supf>v4si): Likewise.
	(mve_vshlcq_<supf><mode>): Likewise.
	(mve_vshlcq_m_<supf><mode>): Likewise.
	(mve_vshrq_m_n_<supf><mode>): Likewise.
	(mve_vshrq_n_<supf><mode>): Likewise.
	(mve_vstrbq_<supf><mode>): Likewise.
	(mve_vstrbq_p_<supf><mode>): Likewise.
	(mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
	(mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrdq_scatter_base_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
	(mve_vstrhq_<supf><mode>): Likewise.
	(mve_vstrhq_fv8hf): Likewise.
	(mve_vstrhq_p_<supf><mode>): Likewise.
	(mve_vstrhq_p_fv8hf): Likewise.
	(mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
	(mve_vstrwq_<supf>v4si): Likewise.
	(mve_vstrwq_fv4sf): Likewise.
	(mve_vstrwq_p_<supf>v4si): Likewise.
	(mve_vstrwq_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.

1 files changed, 2 insertions, 1 deletions

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index dac8885..ff1c27a 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -366,7 +366,8 @@
   "@
    <mve_insn>.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
    * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode), true);"
-  [(set_attr "type" "neon_shift_reg<q>, neon_shift_imm<q>")]
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_<supf><mode>"))
+  (set_attr "type" "neon_shift_reg<q>, neon_shift_imm<q>")]
 )
 
 (define_expand "vashl<mode>3"