[Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size

In the AArch64 backend and scheduling models there is some confusion as to
what the load1/load2 etc. scheduling types refer to. This leads to us using
load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit
loads in AArch32 and 128-bit loads in AArch64. That leads to an undesirable
confusion in scheduling.

Fixing it is easy, but mechanical and boring. Essentially,

  s/load1/load_4/
  s/load2/load_8/
  s/load3/load_12/
  s/load4/load_16/
  s/store1/store_4/
  s/store2/store_8/
  s/store3/store_12/
  s/store4/store_16/

Across all sorts of pipeline models, and the two backends.

I have intentionally not modified any of the patterns which now look obviously
incorrect. I'll be doing a second pass over the AArch64 back-end in patch
2/2 which will fix these bugs.

---
gcc/

	* config/arm/types.md (type): Rename load1/2/3/4 to load_4/8/12/16
	and store1/2/3/4 to store_4/8/12/16.
	* config/aarch64/aarch64.md: Update for rename.
	* config/arm/arm.md: Likewise.: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/thumb1.md: Likewise.
	* config/arm/thumb2.md: Likewise.
	* config/arm/vfp.md: Likewise.
	* config/arm/arm-generic.md: Likewise.
	* config/arm/arm1020e.md: Likewise.
	* config/arm/arm1026ejs.md: Likewise.
	* config/arm/arm1136jfs.md: Likewise.
	* config/arm/arm926ejs.md: Likewise.
	* config/arm/cortex-a15.md: Likewise.
	* config/arm/cortex-a17.md: Likewise.
	* config/arm/cortex-a5.md: Likewise.
	* config/arm/cortex-a53.md: Likewise.
	* config/arm/cortex-a57.md: Likewise.
	* config/arm/cortex-a7.md: Likewise.
	* config/arm/cortex-a8.md: Likewise.
	* config/arm/cortex-a9.md: Likewise.
	* config/arm/cortex-m4.md: Likewise.
	* config/arm/cortex-m7.md: Likewise.
	* config/arm/cortex-r4.md: Likewise.
	* config/arm/exynos-m1.md: Likewise.
	* config/arm/fa526.md: Likewise.
	* config/arm/fa606te.md: Likewise.
	* config/arm/fa626te.md: Likewise.
	* config/arm/fa726te.md: Likewise.
	* config/arm/fmp626.md: Likewise.
	* config/arm/iwmmxt.md: Likewise.
	* config/arm/ldmstm.md: Likewise.
	* config/arm/marvell-pj4.md: Likewise.
	* config/arm/xgene1.md: Likewise.
	* config/aarch64/thunderx.md: Likewise.
	* config/aarch64/thunderx2t99.md: Likewise.
	* config/aarch64/falkor.md: Likewise.

From-SVN: r252025

1 files changed, 9 insertions, 9 deletions

diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index f162fc7..5d196a6 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -650,7 +650,7 @@
     }
   }"
   [(set_attr "length" "4,4,6,6,2,2,6,4,4")
-   (set_attr "type" "multiple,multiple,multiple,multiple,load2,store2,load2,store2,multiple")
+   (set_attr "type" "multiple,multiple,multiple,multiple,load_8,store_8,load_8,store_8,multiple")
    (set_attr "arch" "t1,t1,t1,v8mb,t1,t1,t1,t1,t1")
    (set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")]
 )
@@ -673,7 +673,7 @@
    str\\t%1, %0
    mov\\t%0, %1"
   [(set_attr "length" "2,2,4,4,4,2,2,2,2,2")
-   (set_attr "type" "mov_reg,mov_imm,mov_imm,multiple,multiple,load1,store1,load1,store1,mov_reg")
+   (set_attr "type" "mov_reg,mov_imm,mov_imm,multiple,multiple,load_4,store_4,load_4,store_4,mov_reg")
    (set_attr "pool_range" "*,*,*,*,*,*,*,1018,*,*")
    (set_attr "arch" "t1,t1,v8mb,t1,t1,t1,t1,t1,t1,t1")
    (set_attr "conds" "set,clob,nocond,*,*,nocond,nocond,nocond,nocond,nocond")])
@@ -789,7 +789,7 @@
       return \"ldrh	%0, %1\";
     }"
   [(set_attr "length" "2,4,2,2,2,2,4")
-   (set_attr "type" "alus_imm,load1,store1,mov_reg,mov_reg,mov_imm,mov_imm")
+   (set_attr "type" "alus_imm,load_4,store_4,mov_reg,mov_reg,mov_imm,mov_imm")
    (set_attr "arch" "t1,t1,t1,t1,t1,t1,v8mb")
    (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob,nocond")])
 
@@ -824,7 +824,7 @@
    mov\\t%0, %1
    movs\\t%0, %1"
   [(set_attr "length" "2")
-   (set_attr "type" "alu_imm,load1,store1,mov_reg,mov_imm,mov_imm")
+   (set_attr "type" "alu_imm,load_4,store_4,mov_reg,mov_imm,mov_imm")
    (set_attr "pool_range" "*,32,*,*,*,*")
    (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
 
@@ -860,7 +860,7 @@
     }
   "
   [(set_attr "length" "2")
-   (set_attr "type" "mov_reg,load1,store1,mov_reg,mov_reg")
+   (set_attr "type" "mov_reg,load_4,store_4,mov_reg,mov_reg")
    (set_attr "pool_range" "*,1018,*,*,*")
    (set_attr "conds" "clob,nocond,nocond,nocond,nocond")])
 ;;; ??? This should have alternatives for constants.
@@ -879,7 +879,7 @@
    mov\\t%0, %1
    mov\\t%0, %1"
   [(set_attr "length" "2")
-   (set_attr "type" "alus_imm,load1,store1,load1,store1,mov_reg,mov_reg")
+   (set_attr "type" "alus_imm,load_4,store_4,load_4,store_4,mov_reg,mov_reg")
    (set_attr "pool_range" "*,*,*,1018,*,*,*")
    (set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond,nocond")]
 )
@@ -921,7 +921,7 @@
     }
   "
   [(set_attr "length" "4,2,2,6,4,4")
-   (set_attr "type" "multiple,load2,store2,load2,store2,multiple")
+   (set_attr "type" "multiple,load_8,store_8,load_8,store_8,multiple")
    (set_attr "pool_range" "*,*,*,1018,*,*")]
 )
 
@@ -947,7 +947,7 @@
   [(set_attr "length" "4")
    ; This isn't entirely accurate...  It loads as well, but in terms of
    ; scheduling the following insn it is better to consider it as a store
-   (set_attr "type" "store3")]
+   (set_attr "type" "store_12")]
 )
 
 (define_insn "movmem8b"
@@ -966,7 +966,7 @@
   [(set_attr "length" "4")
    ; This isn't entirely accurate...  It loads as well, but in terms of
    ; scheduling the following insn it is better to consider it as a store
-   (set_attr "type" "store2")]
+   (set_attr "type" "store_8")]
 )