diff options
| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2013-06-06 12:59:04 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2013-06-06 12:59:04 +0000 |
| commit | 12b4e7ef7497b653d6e925649a230b76a4cf241d (patch) | |
| tree | daad67835e6145aaa72d6c9465aaba80167a5019 /gcc/config/arm/sync.md | |
| parent | 15d16c8aeb03601b9a9e09c79abe58bbac4760fd (diff) | |
| download | gcc-12b4e7ef7497b653d6e925649a230b76a4cf241d.zip gcc-12b4e7ef7497b653d6e925649a230b76a4cf241d.tar.gz gcc-12b4e7ef7497b653d6e925649a230b76a4cf241d.tar.bz2 | |
sync.md (atomic_loaddi_1): Disable predication for arm_restrict_it.
2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/sync.md (atomic_loaddi_1):
Disable predication for arm_restrict_it.
(arm_load_exclusive<mode>): Likewise.
(arm_load_exclusivesi): Likewise.
(arm_load_exclusivedi): Likewise.
(arm_load_acquire_exclusive<mode>): Likewise.
(arm_load_acquire_exclusivesi): Likewise.
(arm_load_acquire_exclusivedi): Likewise.
(arm_store_exclusive<mode>): Likewise.
(arm_store_exclusive<mode>): Likewise.
(arm_store_release_exclusivedi): Likewise.
(arm_store_release_exclusive<mode>): Likewise.
From-SVN: r199733
Diffstat (limited to 'gcc/config/arm/sync.md')
| -rw-r--r-- | gcc/config/arm/sync.md | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 9802348..8f7bd71 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -124,7 +124,8 @@ UNSPEC_LL))] "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN" "ldrexd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_expand "atomic_compare_and_swap<mode>" [(match_operand:SI 0 "s_register_operand" "") ;; bool out @@ -361,7 +362,8 @@ VUNSPEC_LL)))] "TARGET_HAVE_LDREXBH" "ldrex<sync_sfx>%?\t%0, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_acquire_exclusive<mode>" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -371,7 +373,8 @@ VUNSPEC_LAX)))] "TARGET_HAVE_LDACQ" "ldaex<sync_sfx>%?\\t%0, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_exclusivesi" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -380,7 +383,8 @@ VUNSPEC_LL))] "TARGET_HAVE_LDREX" "ldrex%?\t%0, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_acquire_exclusivesi" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -389,7 +393,8 @@ VUNSPEC_LAX))] "TARGET_HAVE_LDACQ" "ldaex%?\t%0, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_exclusivedi" [(set (match_operand:DI 0 "s_register_operand" "=r") @@ -398,7 +403,8 @@ VUNSPEC_LL))] "TARGET_HAVE_LDREXD" "ldrexd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_load_acquire_exclusivedi" [(set (match_operand:DI 0 "s_register_operand" "=r") @@ -407,7 +413,8 @@ VUNSPEC_LAX))] "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" "ldaexd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_store_exclusive<mode>" [(set (match_operand:SI 0 "s_register_operand" "=&r") @@ -431,7 +438,8 @@ } return "strex<sync_sfx>%?\t%0, %2, %C1"; } - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_store_release_exclusivedi" [(set (match_operand:SI 0 "s_register_operand" "=&r") @@ -448,7 +456,8 @@ operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); return "stlexd%?\t%0, %2, %3, %C1"; } - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "arm_store_release_exclusive<mode>" [(set (match_operand:SI 0 "s_register_operand" "=&r") @@ -459,4 +468,5 @@ VUNSPEC_SLX))] "TARGET_HAVE_LDACQ" "stlex<sync_sfx>%?\t%0, %2, %C1" - [(set_attr "predicable" "yes")]) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) |