[ARM] Implement support for ACLE Coprocessor CDP intrinsics

gcc/ChangeLog:
2017-01-06  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm.md (<cdp>): New.
	* config/arm/arm.c (neon_const_bounds): Rename this ...
	(arm_const_bounds): ... this.
	(arm_coproc_builtin_available): New.
	* config/arm/arm-builtins.c (SIMD_MAX_BUILTIN_ARGS): Increase.
	(arm_type_qualifiers): Add 'qualifier_unsigned_immediate'.
	(CDP_QUALIFIERS): Define to...
	(arm_cdp_qualifiers): ... this. New.
	(void_UP): Define.
	(arm_expand_builtin_args): Add case for 6 arguments.
	* config/arm/arm-protos.h (neon_const_bounds): Rename this ...
	(arm_const_bounds): ... this.
	(arm_coproc_builtin_available): New.
	* config/arm/arm_acle.h (__arm_cdp): New.
	(__arm_cdp2): New.
	* config/arm/arm_acle_builtins.def (cdp): New.
	(cdp2): New.
	* config/arm/iterators.md (CDPI,CDP,cdp): New.
	* config/arm/neon.md: Rename all 'neon_const_bounds' to
	'arm_const_bounds'.
	* config/arm/types.md (coproc): New.
	* config/arm/unspecs.md (VUNSPEC_CDP, VUNSPEC_CDP2): New.
	* gcc/doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics.
	* gcc/doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok,
	arm_coproc3_ok, arm_coproc4_ok): Document new effective targets.

gcc/testsuite/ChangeLog:
2017-01-06  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/acle/acle.exp: Run tests for different options
	and make sure fat-lto-objects is used such that we can still do
	assemble scans.
	* gcc.target/arm/acle/cdp.c: New.
	* gcc.target/arm/acle/cdp2.c: New.
	* lib/target-supports.exp (check_effective_target_arm_coproc1_ok): New.
	(check_effective_target_arm_coproc1_ok_nocache): New.
	(check_effective_target_arm_coproc2_ok): New.
	(check_effective_target_arm_coproc2_ok_nocache): New.
	(check_effective_target_arm_coproc3_ok): New.
	(check_effective_target_arm_coproc3_ok_nocache): New.
	(check_effective_target_arm_coproc4_ok): New.
	(check_effective_target_arm_coproc4_ok_nocache): New.

From-SVN: r244172

1 files changed, 16 insertions, 16 deletions

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 40f3a32..cf281df 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -3654,7 +3654,7 @@ if (BYTES_BIG_ENDIAN)
 			  VCVT_US_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 1, 33);
+  arm_const_bounds (operands[2], 1, 33);
   return "vcvt.<sup>%#32.f32\t%<V_reg>0, %<V_reg>1, %2";
 }
   [(set_attr "type" "neon_fp_to_int_<V_elem_ch><q>")]
@@ -3668,7 +3668,7 @@ if (BYTES_BIG_ENDIAN)
     VCVT_US_N))]
   "TARGET_NEON_FP16INST"
 {
-  neon_const_bounds (operands[2], 0, 17);
+  arm_const_bounds (operands[2], 0, 17);
   return "vcvt.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1, %2";
 }
  [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
@@ -3681,7 +3681,7 @@ if (BYTES_BIG_ENDIAN)
 			  VCVT_US_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 1, 33);
+  arm_const_bounds (operands[2], 1, 33);
   return "vcvt.f32.<sup>%#32\t%<V_reg>0, %<V_reg>1, %2";
 }
   [(set_attr "type" "neon_int_to_fp_<V_elem_ch><q>")]
@@ -3695,7 +3695,7 @@ if (BYTES_BIG_ENDIAN)
     VCVT_US_N))]
  "TARGET_NEON_FP16INST"
 {
-  neon_const_bounds (operands[2], 0, 17);
+  arm_const_bounds (operands[2], 0, 17);
   return "vcvt.f16.<sup>%#16\t%<V_reg>0, %<V_reg>1, %2";
 }
  [(set_attr "type" "neon_int_to_fp_<VH_elem_ch><q>")]
@@ -4300,7 +4300,7 @@ if (BYTES_BIG_ENDIAN)
                      UNSPEC_VEXT))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
+  arm_const_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
   return "vext.<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2, %3";
 }
   [(set_attr "type" "neon_ext<q>")]
@@ -4397,7 +4397,7 @@ if (BYTES_BIG_ENDIAN)
                       VSHR_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) + 1);
+  arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) + 1);
   return "v<shift_op>.<sup>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
 }
   [(set_attr "type" "neon_shift_imm<q>")]
@@ -4411,7 +4411,7 @@ if (BYTES_BIG_ENDIAN)
                            VSHRN_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
+  arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
   return "v<shift_op>.<V_if_elem>\t%P0, %q1, %2";
 }
   [(set_attr "type" "neon_shift_imm_narrow_q")]
@@ -4425,7 +4425,7 @@ if (BYTES_BIG_ENDIAN)
                            VQSHRN_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
+  arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
   return "v<shift_op>.<sup>%#<V_sz_elem>\t%P0, %q1, %2";
 }
   [(set_attr "type" "neon_sat_shift_imm_narrow_q")]
@@ -4439,7 +4439,7 @@ if (BYTES_BIG_ENDIAN)
                            VQSHRUN_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
+  arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
   return "v<shift_op>.<V_s_elem>\t%P0, %q1, %2";
 }
   [(set_attr "type" "neon_sat_shift_imm_narrow_q")]
@@ -4452,7 +4452,7 @@ if (BYTES_BIG_ENDIAN)
                       UNSPEC_VSHL_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
+  arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
   return "vshl.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %2";
 }
   [(set_attr "type" "neon_shift_imm<q>")]
@@ -4465,7 +4465,7 @@ if (BYTES_BIG_ENDIAN)
                       VQSHL_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
+  arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
   return "vqshl.<sup>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
 }
   [(set_attr "type" "neon_sat_shift_imm<q>")]
@@ -4478,7 +4478,7 @@ if (BYTES_BIG_ENDIAN)
                       UNSPEC_VQSHLU_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
+  arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
   return "vqshlu.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %2";
 }
   [(set_attr "type" "neon_sat_shift_imm<q>")]
@@ -4492,7 +4492,7 @@ if (BYTES_BIG_ENDIAN)
   "TARGET_NEON"
 {
   /* The boundaries are: 0 < imm <= size.  */
-  neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode) + 1);
+  arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode) + 1);
   return "vshll.<sup>%#<V_sz_elem>\t%q0, %P1, %2";
 }
   [(set_attr "type" "neon_shift_imm_long")]
@@ -4507,7 +4507,7 @@ if (BYTES_BIG_ENDIAN)
                       VSRA_N))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
+  arm_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
   return "v<shift_op>.<sup>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
 }
   [(set_attr "type" "neon_shift_acc<q>")]
@@ -4521,7 +4521,7 @@ if (BYTES_BIG_ENDIAN)
                       UNSPEC_VSRI))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
+  arm_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
   return "vsri.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
 }
   [(set_attr "type" "neon_shift_reg<q>")]
@@ -4535,7 +4535,7 @@ if (BYTES_BIG_ENDIAN)
                       UNSPEC_VSLI))]
   "TARGET_NEON"
 {
-  neon_const_bounds (operands[3], 0, neon_element_bits (<MODE>mode));
+  arm_const_bounds (operands[3], 0, neon_element_bits (<MODE>mode));
   return "vsli.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
 }
   [(set_attr "type" "neon_shift_reg<q>")]