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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2015-11-20 15:15:31 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2015-11-20 15:15:31 +0000 |
| commit | 88fdc9a66e4b14aef5aa4b873223e4d081a8824c (patch) | |
| tree | d0a3239ba96cd38b33d1606c7527cdc633c7ad43 /gcc/config/arm/arm.md | |
| parent | 1add8de5b7092621ae7271e19e9ff4a371a303e8 (diff) | |
| download | gcc-88fdc9a66e4b14aef5aa4b873223e4d081a8824c.zip gcc-88fdc9a66e4b14aef5aa4b873223e4d081a8824c.tar.gz gcc-88fdc9a66e4b14aef5aa4b873223e4d081a8824c.tar.bz2 | |
[ARM] PR 68149 Fix ICE in unaligned_loaddi split
PR target/68149
* config/arm/arm.md (unaligned_loaddi): Delete.
(unaligned_storedi): Likewise.
* config/arm/arm.c (gen_movmem_ldrd_strd): Don't generate
unaligned DImode memory ops. Instead perform two back-to-back
unaligned SImode ops.
From-SVN: r230663
Diffstat (limited to 'gcc/config/arm/arm.md')
| -rw-r--r-- | gcc/config/arm/arm.md | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 73c3088..227a9bd 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4277,59 +4277,6 @@ (set_attr "predicable_short_it" "yes,no") (set_attr "type" "store1")]) -;; Unaligned double-word load and store. -;; Split after reload into two unaligned single-word accesses. -;; It prevents lower_subreg from splitting some other aligned -;; double-word accesses too early. Used for internal memcpy. - -(define_insn_and_split "unaligned_loaddi" - [(set (match_operand:DI 0 "s_register_operand" "=l,r") - (unspec:DI [(match_operand:DI 1 "memory_operand" "o,o")] - UNSPEC_UNALIGNED_LOAD))] - "unaligned_access && TARGET_32BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_LOAD)) - (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_LOAD))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - - /* If the first destination register overlaps with the base address, - swap the order in which the loads are emitted. */ - if (reg_overlap_mentioned_p (operands[0], operands[1])) - { - std::swap (operands[1], operands[3]); - std::swap (operands[0], operands[2]); - } - } - [(set_attr "arch" "t2,any") - (set_attr "length" "4,8") - (set_attr "predicable" "yes") - (set_attr "type" "load2")]) - -(define_insn_and_split "unaligned_storedi" - [(set (match_operand:DI 0 "memory_operand" "=o,o") - (unspec:DI [(match_operand:DI 1 "s_register_operand" "l,r")] - UNSPEC_UNALIGNED_STORE))] - "unaligned_access && TARGET_32BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_STORE)) - (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_STORE))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } - [(set_attr "arch" "t2,any") - (set_attr "length" "4,8") - (set_attr "predicable" "yes") - (set_attr "type" "store2")]) - (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") |