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| author | Mihail Ionescu <mihail.ionescu@arm.com> | 2020-01-17 17:56:41 +0000 |
|---|---|---|
| committer | Mihail Ionescu <mihail.ionescu@arm.com> | 2020-01-17 18:50:38 +0000 |
| commit | 60d616b1f6deffcc57a4114f1a31559a17a3923c (patch) | |
| tree | 2249d70f1506a4236544f25cb590578bfb3fceec /gcc/config/arm/arm.c | |
| parent | 674dcc3f738c4be2bc7d51d72d98fb1c0d2ebea2 (diff) | |
| download | gcc-60d616b1f6deffcc57a4114f1a31559a17a3923c.zip gcc-60d616b1f6deffcc57a4114f1a31559a17a3923c.tar.gz gcc-60d616b1f6deffcc57a4114f1a31559a17a3923c.tar.bz2 | |
[GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline
This patch is adding the following instructions:
ASRL (reg)
LSLL (reg)
*** gcc/ChangeLog ***
2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
Sudakshina Das <sudi.das@arm.com>
* config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
(ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
* config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
register pairs for doubleword quantities for ARMv8.1M-Mainline.
* config/arm/thumb2.md (thumb2_asrl): New.
(thumb2_lsll): Likewise.
2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
Sudakshina Das <sudi.das@arm.com>
* gcc.target/arm/armv8_1m-shift-reg_1.c: New test.
Diffstat (limited to 'gcc/config/arm/arm.c')
| -rw-r--r-- | gcc/config/arm/arm.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 57099cb..6ead410 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -24906,14 +24906,16 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) /* We allow almost any value to be stored in the general registers. Restrict doubleword quantities to even register pairs in ARM state - so that we can use ldrd. Do not allow very large Neon structure - opaque modes in general registers; they would use too many. */ + so that we can use ldrd. The same restriction applies for MVE + in order to support Armv8.1-M Mainline instructions. + Do not allow very large Neon structure opaque modes in general + registers; they would use too many. */ if (regno <= LAST_ARM_REGNUM) { if (ARM_NUM_REGS (mode) > 4) return false; - if (TARGET_THUMB2) + if (TARGET_THUMB2 && !TARGET_HAVE_MVE) return true; return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); |