arc-common.c (arc_handle_option): Handle ARCv2 options.

2015-11-11  Claudiu Zissulescu  <claziss@synopsys.com>

	* common/config/arc/arc-common.c (arc_handle_option): Handle ARCv2
	options.
	* config/arc/arc-opts.h: Add ARCv2 CPUs.
	* config/arc/arc-protos.h (arc_secondary_reload_conv): Prototype.
	* config/arc/arc.c (arc_secondary_reload): Handle subreg (reg)
	situation, and store instructions with large offsets.
	(arc_secondary_reload_conv): New function.
	(arc_init): Add ARCv2 options.
	(arc_conditional_register_usage): Select the proper register usage
	for ARCv2 processors.
	(arc_handle_interrupt_attribute): ILINK2 is only valid for ARCv1
	architecture.
	(arc_compute_function_type): Likewise.
	(arc_print_operand): Handle new ARCv2 punctuation characters.
	(arc_return_in_memory): ARCv2 ABI returns in registers up to 16
	bytes.
	(workaround_arc_anomaly, arc_asm_insn_p, arc_loop_hazard): New
	function.
	(arc_reorg, arc_hazard): Use it.
	* config/arc/arc.h (TARGET_CPU_CPP_BUILTINS): Define __HS__ and
	__EM__.
	(ASM_SPEC): Add ARCv2 options.
	(TARGET_NORM): ARC HS has norm instructions by default.
	(TARGET_OPTFPE): Use optimized floating point emulation for ARC
	HS.
	(TARGET_AT_DBR_CONDEXEC): Only for ARC600 family.
	(TARGET_EM, TARGET_HS, TARGET_V2, TARGET_MPYW, TARGET_MULTI):
	Define.
	(SIGNED_INT16, TARGET_MPY, TARGET_ARC700_MPY, TARGET_ANY_MPY):
	Likewise.
	(TARGET_ARC600_FAMILY, TARGET_ARCOMPACT_FAMILY): Likewise.
	(TARGET_LP_WR_INTERLOCK): Likewise.
	* config/arc/arc.md
	(commutative_binary_mult_comparison_result_used, movsicc_insn)
	(mulsi3, mulsi3_600_lib, mulsidi3, mulsidi3_700, mulsi3_highpart)
	(umulsi3_highpart_i, umulsi3_highpart_int, umulsi3_highpart)
	(umulsidi3, umulsidi3_700, cstoresi4, simple_return, p_return_i):
	Use it for ARCv2.
	(mulhisi3, mulhisi3_imm, mulhisi3_reg, umulhisi3, umulhisi3_imm)
	(umulhisi3_reg, umulhisi3_reg, mulsi3_v2, nopv, bswapsi2)
	(prefetch, divsi3, udivsi3 modsi3, umodsi3, arcset, arcsetltu)
	(arcsetgeu, arcsethi, arcsetls, reload_*_load, reload_*_store)
	(extzvsi): New pattern.
	* config/arc/arc.opt: New ARCv2 options.
	* config/arc/arcEM.md: New file.
	* config/arc/arcHS.md: Likewise.
	* config/arc/constraints.md (C3p): New constraint, accepts 1 and 2
	values.
	(Cm2): A signed 9-bit integer constant constraint.
	(C62): An unsigned 6-bit integer constant constraint.
	(C16): A signed 16-bit integer constant constraint.
	* config/arc/predicates.md (mult_operator): Add ARCv2 processort.
	(short_const_int_operand): New predicate.
	* config/arc/t-arc-newlib: Add ARCv2 multilib options.
	* doc/invoke.texi: Add documentation for -mcpu=<archs/arcem>
	-mcode-density and -mdiv-rem.

From-SVN: r230156

1 files changed, 93 insertions, 0 deletions

diff --git a/gcc/config/arc/arcEM.md b/gcc/config/arc/arcEM.md
new file mode 100644
index 0000000..a72d250
--- /dev/null
+++ b/gcc/config/arc/arcEM.md
@@ -0,0 +1,93 @@
+;; DFA scheduling description of the Synopsys DesignWare ARC EM cpu
+;; for GNU C compiler
+;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
+;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com>
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "ARCEM")
+
+(define_cpu_unit "em_issue, ld_st, mul_em, divrem_em" "ARCEM")
+
+(define_insn_reservation "em_data_load" 2
+  (and (match_test "TARGET_EM")
+       (eq_attr "type" "load"))
+  "em_issue+ld_st,nothing")
+
+(define_insn_reservation "em_data_store" 1
+  (and (match_test "TARGET_EM")
+       (eq_attr "type" "store"))
+  "em_issue+ld_st")
+
+;; Multipliers options
+(define_insn_reservation "mul_em_mpyw_1" 1
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option > 0")
+       (match_test "arc_mpy_option <= 2")
+       (eq_attr "type" "mul16_em"))
+  "em_issue+mul_em")
+
+(define_insn_reservation "mul_em_mpyw_2" 2
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option > 2")
+       (match_test "arc_mpy_option <= 5")
+       (eq_attr "type" "mul16_em"))
+  "em_issue+mul_em, nothing")
+
+(define_insn_reservation "mul_em_mpyw_4" 4
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option == 6")
+       (eq_attr "type" "mul16_em"))
+  "em_issue+mul_em, mul_em*3")
+
+(define_insn_reservation "mul_em_multi_wlh1" 1
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option == 2")
+       (eq_attr "type" "multi,umulti"))
+  "em_issue+mul_em")
+
+(define_insn_reservation "mul_em_multi_wlh2" 2
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option == 3")
+       (eq_attr "type" "multi,umulti"))
+  "em_issue+mul_em, nothing")
+
+(define_insn_reservation "mul_em_multi_wlh3" 3
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option == 4")
+       (eq_attr "type" "multi,umulti"))
+  "em_issue+mul_em, mul_em*2")
+
+;; FIXME! Make the difference between MPY and MPYM for WLH4
+(define_insn_reservation "mul_em_multi_wlh4" 4
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option == 5")
+       (eq_attr "type" "multi,umulti"))
+  "em_issue+mul_em, mul_em*4")
+
+(define_insn_reservation "mul_em_multi_wlh5" 9
+  (and (match_test "TARGET_EM")
+       (match_test "arc_mpy_option == 6")
+       (eq_attr "type" "multi,umulti"))
+  "em_issue+mul_em, mul_em*8")
+
+;; Radix-4 divider timing
+(define_insn_reservation "em_divrem" 3
+  (and (match_test "TARGET_EM")
+       (match_test "TARGET_DIVREM")
+       (eq_attr "type" "div_rem"))
+  "em_issue+mul_em+divrem_em, (mul_em+divrem_em)*2")