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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-05-02 10:54:34 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2016-05-02 10:54:34 +0200 |
| commit | fc1c2d0482260c80cfe8363f96ace9a57f10cbf4 (patch) | |
| tree | c40e671c5b2a36bde4b5873c1bb266562c0fc4a5 /gcc/config/arc/arc.h | |
| parent | 02673c66c6477d1212a49a602f74c624267dda29 (diff) | |
| download | gcc-fc1c2d0482260c80cfe8363f96ace9a57f10cbf4.zip gcc-fc1c2d0482260c80cfe8363f96ace9a57f10cbf4.tar.gz gcc-fc1c2d0482260c80cfe8363f96ace9a57f10cbf4.tar.bz2 | |
[ARC] Add new ARCv2 instructions.
gcc/
2016-05-02 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (compact_memory_operand_p): Declare.
* config/arc/arc.c (arc_output_commutative_cond_exec): Consider
bmaskn instruction.
(arc_dwarf_register_span): Remove enum keyword.
(compact_memory_operand_p): New function.
* config/arc/arc.h (reg_class): Add code density register classes.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
* config/arc/arc.md (*movqi_insn): Add code density instructions.
(*movhi_insn, *movsi_insn, *movsf_insn): Likewise.
(*extendhisi2_i, andsi3_i, cmpsi_cc_insn_mixed): Likewise.
(*cmpsi_cc_c_insn, *movsi_ne): Likewise.
* config/arc/constraints.md (C2p, Uts, Cm1, Cm3, Ucd): New
constraints.
(h, Rcd, Rsd, Rzd): New register constraints.
(T): Use compact_memory_operand_p function.
* config/arc/predicates.md (compact_load_memory_operand): Remove.
From-SVN: r235707
Diffstat (limited to 'gcc/config/arc/arc.h')
| -rw-r--r-- | gcc/config/arc/arc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index bc14d11..f6b85ea 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -674,6 +674,9 @@ enum reg_class WRITABLE_CORE_REGS, /* 'w' */ CHEAP_CORE_REGS, /* 'c' */ ALL_CORE_REGS, /* 'Rac' */ + R0R3_CD_REGS, /* 'Rcd' */ + R0R1_CD_REGS, /* 'Rsd' */ + AC16_H_REGS, /* 'h' */ ALL_REGS, LIM_REG_CLASSES }; @@ -700,6 +703,9 @@ enum reg_class "MPY_WRITABLE_CORE_REGS", \ "WRITABLE_CORE_REGS", \ "CHEAP_CORE_REGS", \ + "R0R3_CD_REGS", \ + "R0R1_CD_REGS", \ + "AC16_H_REGS", \ "ALL_CORE_REGS", \ "ALL_REGS" \ } @@ -732,6 +738,9 @@ enum reg_class {0xffffffff, 0xd0000000, 0x00000000, 0x00000000, 0x00000000}, /* 'w', r0-r31, r60 */ \ {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'c', r0-r60, ap, pcl */ \ {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'Rac', r0-r60, ap, pcl */ \ + {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd', r0-r3 */ \ + {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd', r0-r1 */ \ + {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h', r0-28, r30 */ \ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* All Registers */ \ } |