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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2020-12-11 18:27:21 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2020-12-11 18:29:56 +0200 |
| commit | dfbe642c97f7f430926cb6b33cd5c20b42c85573 (patch) | |
| tree | e633bbba7f9eda9b709041cda10acba72dd8001f /gcc/config/arc/arc.c | |
| parent | 1c6b86b50d4624e2bb665378a424f99a67831693 (diff) | |
| download | gcc-dfbe642c97f7f430926cb6b33cd5c20b42c85573.zip gcc-dfbe642c97f7f430926cb6b33cd5c20b42c85573.tar.gz gcc-dfbe642c97f7f430926cb6b33cd5c20b42c85573.tar.bz2 | |
arc: Refurbish adc/sbc patterns
The adc/sbc patterns were unecessary spliting, remove that and
associated functions.
gcc/
2020-12-11 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
it.
(arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
* config/arc/arc.c (arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
(arc_scheduling_not_expected): Likewise.
* config/arc/arc.md: Convert adc/sbc patterns to simple
instruction definitions.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Diffstat (limited to 'gcc/config/arc/arc.c')
| -rw-r--r-- | gcc/config/arc/arc.c | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index eabc122..b80bb9b 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -10299,59 +10299,6 @@ arc_attr_type (rtx_insn *insn) return get_attr_type (insn); } -/* Return true if insn sets the condition codes. */ - -bool -arc_sets_cc_p (rtx_insn *insn) -{ - if (NONJUMP_INSN_P (insn)) - if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) - insn = seq->insn (seq->len () - 1); - return arc_attr_type (insn) == TYPE_COMPARE; -} - -/* Return true if INSN is an instruction with a delay slot we may want - to fill. */ - -bool -arc_need_delay (rtx_insn *insn) -{ - rtx_insn *next; - - if (!flag_delayed_branch) - return false; - /* The return at the end of a function needs a delay slot. */ - if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE - && (!(next = next_active_insn (insn)) - || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE) - && arc_attr_type (next) == TYPE_RETURN)) - && (!TARGET_PAD_RETURN - || (prev_active_insn (insn) - && prev_active_insn (prev_active_insn (insn)) - && prev_active_insn (prev_active_insn (prev_active_insn (insn)))))) - return true; - if (NONJUMP_INSN_P (insn) - ? (GET_CODE (PATTERN (insn)) == USE - || GET_CODE (PATTERN (insn)) == CLOBBER - || GET_CODE (PATTERN (insn)) == SEQUENCE) - : JUMP_P (insn) - ? (GET_CODE (PATTERN (insn)) == ADDR_VEC - || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) - : !CALL_P (insn)) - return false; - return num_delay_slots (insn) != 0; -} - -/* Return true if the scheduling pass(es) has/have already run, - i.e. where possible, we should try to mitigate high latencies - by different instruction selection. */ - -bool -arc_scheduling_not_expected (void) -{ - return cfun->machine->arc_reorg_started; -} - /* Code has a minimum p2 alignment of 1, which we must restore after an ADDR_DIFF_VEC. */ |