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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2016-02-16 15:59:51 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2016-02-16 15:59:51 +0000 |
| commit | 51b3f0773f84ef1e3aac56e687f67027c3fb070c (patch) | |
| tree | 39708469fbd9679f3dd026e8b68a16ac3ccf243e /gcc/config/aarch64 | |
| parent | e387d491abf516207c9d98ab18c87029ee3a9749 (diff) | |
| download | gcc-51b3f0773f84ef1e3aac56e687f67027c3fb070c.zip gcc-51b3f0773f84ef1e3aac56e687f67027c3fb070c.tar.gz gcc-51b3f0773f84ef1e3aac56e687f67027c3fb070c.tar.bz2 | |
[Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
gcc/
* config/aarch64/aarch64.md
(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
constraints for operand 3.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
From-SVN: r233460
Diffstat (limited to 'gcc/config/aarch64')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 3047841..d8497ab 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3240,7 +3240,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCOND> 3 "register_operand" "w") + (match_operand:<VCOND> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3258,7 +3258,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCOND> 3 "register_operand" "w") + (match_operand:<VCOND> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3278,7 +3278,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCONQ> 3 "register_operand" "w") + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3296,7 +3296,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCONQ> 3 "register_operand" "w") + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" |