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| author | Jakub Jelinek <jakub@redhat.com> | 2021-01-27 20:35:21 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2021-01-27 20:35:21 +0100 |
| commit | 55163419211c6f17e3e22c68304384eba35782a3 (patch) | |
| tree | 51dfb5109fbd6778eb0d29cdc122e8c328241dd1 /gcc/config/aarch64/aarch64.md | |
| parent | 7a279bed24e1b2a628767a60a20f3dcf6f1088cb (diff) | |
| download | gcc-55163419211c6f17e3e22c68304384eba35782a3.zip gcc-55163419211c6f17e3e22c68304384eba35782a3.tar.gz gcc-55163419211c6f17e3e22c68304384eba35782a3.tar.bz2 | |
aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]
The https://gcc.gnu.org/legacy-ml/gcc-patches/2018-07/msg01895.html
patch that introduced this pattern claimed:
Would generate:
combine_balanced_int:
bfxil w0, w1, 0, 16
uxtw x0, w0
ret
But with this patch generates:
combine_balanced_int:
bfxil w0, w1, 0, 16
ret
and it is indeed what it should generate, but it doesn't do that,
it emits bfxil x0, x1, 0, 16
instead which doesn't zero extend from 32 to 64 bits, but preserves
the bits from the destination register.
2021-01-27 Jakub Jelinek <jakub@redhat.com>
PR target/98853
* config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use
%w0, %w1 and %2 instead of %0, %1 and %2.
* gcc.c-torture/execute/pr98853-1.c: New test.
* gcc.c-torture/execute/pr98853-2.c: New test.
Diffstat (limited to 'gcc/config/aarch64/aarch64.md')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 45d9c6a..e599076 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5724,10 +5724,10 @@ { case 0: operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[3]))); - return "bfxil\\t%0, %1, 0, %3"; + return "bfxil\\t%w0, %w1, 0, %3"; case 1: operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[4]))); - return "bfxil\\t%0, %2, 0, %3"; + return "bfxil\\t%w0, %w2, 0, %3"; default: gcc_unreachable (); } |