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| author | liuhongt <hongtao.liu@intel.com> | 2023-08-04 09:27:39 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2023-08-09 14:01:24 +0800 |
| commit | b39f8bdad1c5a2c77b9005f1900cdcb9b66594ad (patch) | |
| tree | 6ffde1c8b84937fcc8e0ea4ff8e370bbcc3cc5b0 /gcc/config/aarch64/aarch64.cc | |
| parent | c8b396243ec5bfa9b541555131df597ebc84b9d0 (diff) | |
| download | gcc-b39f8bdad1c5a2c77b9005f1900cdcb9b66594ad.zip gcc-b39f8bdad1c5a2c77b9005f1900cdcb9b66594ad.tar.gz gcc-b39f8bdad1c5a2c77b9005f1900cdcb9b66594ad.tar.bz2 | |
Workaround possible CPUID bug in Sandy Bridge.
Don't access leaf 7 subleaf 1 unless subleaf 0 says it is
supported via EAX.
Intel documentation says invalid subleaves return 0. We had been
relying on that behavior instead of checking the max sublef number.
It appears that some Sandy Bridge CPUs return at least the subleaf 0
EDX value for subleaf 1. Best guess is that this is a bug in a
microcode patch since all of the bits we're seeing set in EDX were
introduced after Sandy Bridge was originally released.
This is causing avxvnniint16 to be incorrectly enabled with
-march=native on these CPUs.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features): Check
EAX for valid subleaf before use CPUID.
Diffstat (limited to 'gcc/config/aarch64/aarch64.cc')
0 files changed, 0 insertions, 0 deletions