diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-10-17 23:46:33 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-10-17 23:46:33 +0100 |
| commit | 773306e9ef4ea1407f89686eb513a50602493666 (patch) | |
| tree | 385805da3c1f69f88ace1bc12a8ecf7c7b774f1b /gcc/config/aarch64/aarch64.cc | |
| parent | 575858508090b18dcbc176db285c9f55227ca4c0 (diff) | |
| download | gcc-773306e9ef4ea1407f89686eb513a50602493666.zip gcc-773306e9ef4ea1407f89686eb513a50602493666.tar.gz gcc-773306e9ef4ea1407f89686eb513a50602493666.tar.bz2 | |
aarch64: Put LR save slot first in more cases
Now that the prologue and epilogue code iterates over saved
registers in offset order, we can put the LR save slot first
without compromising LDP/STP formation.
This isn't worthwhile when shadow call stacks are enabled, since the
first two registers are also push/pop candidates, and LR cannot be
popped when shadow call stacks are enabled. (LR is instead loaded
first and compared against the shadow stack's value.)
But otherwise, it seems better to put the LR save slot first,
to reduce unnecessary variation with the layout for stack clash
protection.
gcc/
* config/aarch64/aarch64.cc (aarch64_layout_frame): Don't make
the position of the LR save slot dependent on stack clash
protection unless shadow call stacks are enabled.
gcc/testsuite/
* gcc.target/aarch64/test_frame_2.c: Expect x30 to come before x19.
* gcc.target/aarch64/test_frame_4.c: Likewise.
* gcc.target/aarch64/test_frame_7.c: Likewise.
* gcc.target/aarch64/test_frame_10.c: Likewise.
Diffstat (limited to 'gcc/config/aarch64/aarch64.cc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e8b5dfe..62b1ae0 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -8694,7 +8694,7 @@ aarch64_layout_frame (void) allocate_gpr_slot (R29_REGNUM); allocate_gpr_slot (R30_REGNUM); } - else if (flag_stack_clash_protection + else if ((flag_stack_clash_protection || !frame.is_scs_enabled) && known_eq (frame.reg_offset[R30_REGNUM], SLOT_REQUIRED)) /* Put the LR save slot first, since it makes a good choice of probe for stack clash purposes. The idea is that the link register usually |