[AArch64] [SVE] Implement svld1ro intrinsic.

We take no action to ensure the SVE vector size is large enough.  It is
left to the user to check that before compiling this intrinsic or before
running such a program on a machine.

The main difference between ld1ro and ld1rq is in the allowed offsets,
the implementation difference is that ld1ro is implemented using integer
modes since there are no pre-existing vector modes of the relevant size.
Adding new vector modes simply for this intrinsic seems to make the code
less tidy.

Specifications can be found under the "Arm C Language Extensions for
Scalable Vector Extension" title at
https://developer.arm.com/architectures/system-architectures/software-standards/acle

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-protos.h
	(aarch64_sve_ld1ro_operand_p): New.
	* config/aarch64/aarch64-sve-builtins-base.cc
	(class load_replicate): New.
	(class svld1ro_impl): New.
	(class svld1rq_impl): Change to inherit from load_replicate.
	(svld1ro): New sve intrinsic function base.
	* config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
	New DEF_SVE_FUNCTION.
	* config/aarch64/aarch64-sve-builtins-base.h
	(svld1ro): New decl.
	* config/aarch64/aarch64-sve-builtins.cc
	(function_expander::add_mem_operand): Modify assert to allow
	OImode.
	* config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
	pattern.
	* config/aarch64/aarch64.c
	(aarch64_sve_ld1rq_operand_p): Implement in terms of ...
	(aarch64_sve_ld1rq_ld1ro_operand_p): This.
	(aarch64_sve_ld1ro_operand_p): New.
	* config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
	* config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
	* config/aarch64/predicates.md
	(aarch64_sve_ld1ro_operand_{b,h,w,d}): New.

gcc/testsuite/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c: New test.

1 files changed, 23 insertions, 1 deletions

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 16a7898..868a6af 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -1169,7 +1169,7 @@ public:
   }
 };
 
-class svld1rq_impl : public function_base
+class load_replicate : public function_base
 {
 public:
   unsigned int
@@ -1183,7 +1183,11 @@ public:
   {
     return fi.scalar_type (0);
   }
+};
 
+class svld1rq_impl : public load_replicate
+{
+public:
   machine_mode
   memory_vector_mode (const function_instance &fi) const OVERRIDE
   {
@@ -1198,6 +1202,23 @@ public:
   }
 };
 
+class svld1ro_impl : public load_replicate
+{
+public:
+  machine_mode
+  memory_vector_mode (const function_instance &fi) const OVERRIDE
+  {
+    return OImode;
+  }
+
+  rtx
+  expand (function_expander &e) const OVERRIDE
+  {
+    insn_code icode = code_for_aarch64_sve_ld1ro (e.vector_mode (0));
+    return e.use_contiguous_load_insn (icode);
+  }
+};
+
 /* Implements svld2, svld3 and svld4.  */
 class svld234_impl : public full_width_access
 {
@@ -2540,6 +2561,7 @@ FUNCTION (svlasta, svlast_impl, (UNSPEC_LASTA))
 FUNCTION (svlastb, svlast_impl, (UNSPEC_LASTB))
 FUNCTION (svld1, svld1_impl,)
 FUNCTION (svld1_gather, svld1_gather_impl,)
+FUNCTION (svld1ro, svld1ro_impl,)
 FUNCTION (svld1rq, svld1rq_impl,)
 FUNCTION (svld1sb, svld1_extend_impl, (TYPE_SUFFIX_s8))
 FUNCTION (svld1sb_gather, svld1_gather_extend_impl, (TYPE_SUFFIX_s8))