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| author | Jim Wilson <wilson@redhat.com> | 2002-09-20 21:42:25 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2002-09-20 14:42:25 -0700 |
| commit | a9b2f059741b06195e3272143f9a609459d8ca78 (patch) | |
| tree | 4153c004242ecb1aee635758e2f6c7141a996b18 /gcc/combine.c | |
| parent | 27eba3092297b924cce500c1d815cde3a7913eda (diff) | |
| download | gcc-a9b2f059741b06195e3272143f9a609459d8ca78.zip gcc-a9b2f059741b06195e3272143f9a609459d8ca78.tar.gz gcc-a9b2f059741b06195e3272143f9a609459d8ca78.tar.bz2 | |
Fix v850 ICE.
* combine.c (try_combine): When split an instruction pair, where the
first has a sign_extend src, verify that the src and dest modes match.
From-SVN: r57371
Diffstat (limited to 'gcc/combine.c')
| -rw-r--r-- | gcc/combine.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gcc/combine.c b/gcc/combine.c index 2313619..1d6a5b2 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -2316,6 +2316,10 @@ try_combine (i3, i2, i1, new_direct_jump_p) copy. This saves at least one insn, more if register allocation can eliminate the copy. + We cannot do this if the destination of the first assignment is a + condition code register or cc0. We eliminate this case by making sure + the SET_DEST and SET_SRC have the same mode. + We cannot do this if the destination of the second assignment is a register that we have already assumed is zero-extended. Similarly for a SUBREG of such a register. */ @@ -2325,6 +2329,8 @@ try_combine (i3, i2, i1, new_direct_jump_p) && XVECLEN (newpat, 0) == 2 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND + && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) + == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) && GET_CODE (XVECEXP (newpat, 0, 1)) == SET && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) |