diff options
| author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-12-16 14:14:18 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-12-16 14:14:18 +0000 |
| commit | 7e594332e400b26cd2df4a40980d08ffc7fcfc1a (patch) | |
| tree | 7aeb539f672b7290a347caab3491519b27867ab0 /gcc/calls.c | |
| parent | 05210ba63707fd3dc120f0f5a76add5ca172881e (diff) | |
| download | gcc-7e594332e400b26cd2df4a40980d08ffc7fcfc1a.zip gcc-7e594332e400b26cd2df4a40980d08ffc7fcfc1a.tar.gz gcc-7e594332e400b26cd2df4a40980d08ffc7fcfc1a.tar.bz2 | |
Add a gen_int_shift_amount helper function
This patch adds a helper routine that constructs rtxes
for constant shift amounts, given the mode of the value
being shifted. As well as helping with the SVE patches, this
is one step towards allowing CONST_INTs to have a real mode.
One long-standing problem has been to decide what the mode
of a shift count should be for arbitrary rtxes (as opposed to those
directly tied to a target pattern). Realistic choices would be
the mode of the shifted elements, word_mode, QImode, or the same
mode as the shift optabs (in which case what should the mode
be when the target doesn't have a pattern?)
For now the patch picks the mode of the shifted elements,
but with a ??? comment.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* emit-rtl.h (gen_int_shift_amount): Declare.
* emit-rtl.c (gen_int_shift_amount): New function.
* asan.c (asan_emit_stack_protection): Use gen_int_shift_amount
instead of GEN_INT.
* calls.c (shift_return_value): Likewise.
* cse.c (fold_rtx): Likewise.
* dse.c (find_shift_sequence): Likewise.
* expmed.c (init_expmed_one_mode, store_bit_field_1, expand_shift_1)
(expand_shift, expand_smod_pow2): Likewise.
* lower-subreg.c (shift_cost): Likewise.
* optabs.c (expand_superword_shift, expand_doubleword_mult)
(expand_unop, expand_binop, shift_amt_for_vec_perm_mask)
(expand_vec_perm_var): Likewise.
* simplify-rtx.c (simplify_unary_operation_1): Likewise.
(simplify_binary_operation_1): Likewise.
* combine.c (try_combine, find_split_point, force_int_to_mode)
(simplify_shift_const_1, simplify_shift_const): Likewise.
(change_zero_ext): Likewise. Use simplify_gen_binary.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255745
Diffstat (limited to 'gcc/calls.c')
| -rw-r--r-- | gcc/calls.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/gcc/calls.c b/gcc/calls.c index 8ae9899..5f7fdd3 100644 --- a/gcc/calls.c +++ b/gcc/calls.c @@ -2900,15 +2900,17 @@ shift_return_value (machine_mode mode, bool left_p, rtx value) HOST_WIDE_INT shift; gcc_assert (REG_P (value) && HARD_REGISTER_P (value)); - shift = GET_MODE_BITSIZE (GET_MODE (value)) - GET_MODE_BITSIZE (mode); + machine_mode value_mode = GET_MODE (value); + shift = GET_MODE_BITSIZE (value_mode) - GET_MODE_BITSIZE (mode); if (shift == 0) return false; /* Use ashr rather than lshr for right shifts. This is for the benefit of the MIPS port, which requires SImode values to be sign-extended when stored in 64-bit registers. */ - if (!force_expand_binop (GET_MODE (value), left_p ? ashl_optab : ashr_optab, - value, GEN_INT (shift), value, 1, OPTAB_WIDEN)) + if (!force_expand_binop (value_mode, left_p ? ashl_optab : ashr_optab, + value, gen_int_shift_amount (value_mode, shift), + value, 1, OPTAB_WIDEN)) gcc_unreachable (); return true; } |