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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2023-08-04 17:23:56 -0400 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2023-08-04 17:25:30 -0400 |
| commit | 4e87c953d16377457b31b65b6c3268d932e462ab (patch) | |
| tree | 1939101c7e43009547e4705937a0642339a1ab6e /gcc/analyzer/ChangeLog | |
| parent | 021077b94741c9300dfff3a24e95b3ffa3f508a7 (diff) | |
| download | gcc-4e87c953d16377457b31b65b6c3268d932e462ab.zip gcc-4e87c953d16377457b31b65b6c3268d932e462ab.tar.gz gcc-4e87c953d16377457b31b65b6c3268d932e462ab.tar.bz2 | |
[PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
This patch recognizes Zicond patterns when the select pattern
with condition eq or neq to 0 (using eq as an example), namely:
1 rd = (rs2 == 0) ? non-imm : 0
2 rd = (rs2 == 0) ? non-imm : non-imm
3 rd = (rs2 == 0) ? reg : non-imm
4 rd = (rs2 == 0) ? reg : reg
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
more Zicond patterns. Fix whitespace typo.
(riscv_rtx_costs): Remove accidental code duplication.
Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
Diffstat (limited to 'gcc/analyzer/ChangeLog')
0 files changed, 0 insertions, 0 deletions