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| author | Kong Lingling <lingling.kong@intel.com> | 2023-03-23 14:34:36 +0800 |
|---|---|---|
| committer | Hongyu Wang <hongyu.wang@intel.com> | 2023-10-07 16:34:29 +0800 |
| commit | bc4466b94e91f4d2a051a9beba45187e7c23615c (patch) | |
| tree | 4e380e708626b2be7c411855590e7df0c02375b3 /gcc/addresses.h | |
| parent | 7866984ba427dc56a12ee1b8d99feb4927b834b1 (diff) | |
| download | gcc-bc4466b94e91f4d2a051a9beba45187e7c23615c.zip gcc-bc4466b94e91f4d2a051a9beba45187e7c23615c.tar.gz gcc-bc4466b94e91f4d2a051a9beba45187e7c23615c.tar.bz2 | |
[APX EGPR] middle-end: Add insn argument to base_reg_class
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add new macros with insn parameters to base_reg_class
for lra/reload usage.
gcc/ChangeLog:
* addresses.h (base_reg_class): Add insn argument and new macro
INSN_BASE_REG_CLASS.
(regno_ok_for_base_p_1): Add insn argument and new macro
REGNO_OK_FOR_INSN_BASE_P.
(regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1.
* doc/tm.texi: Document INSN_BASE_REG_CLASS and
REGNO_OK_FOR_INSN_BASE_P.
* doc/tm.texi.in: Ditto.
* lra-constraints.cc (process_address_1): Pass insn to
base_reg_class.
(curr_insn_transform): Ditto.
* reload.cc (find_reloads): Ditto.
(find_reloads_address): Ditto.
(find_reloads_address_1): Ditto.
(find_reloads_subreg_address): Ditto.
* reload1.cc (maybe_fix_stack_asms): Ditto.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Diffstat (limited to 'gcc/addresses.h')
| -rw-r--r-- | gcc/addresses.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/gcc/addresses.h b/gcc/addresses.h index 3519c24..2c92927 100644 --- a/gcc/addresses.h +++ b/gcc/addresses.h @@ -28,8 +28,12 @@ inline enum reg_class base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, addr_space_t as ATTRIBUTE_UNUSED, enum rtx_code outer_code ATTRIBUTE_UNUSED, - enum rtx_code index_code ATTRIBUTE_UNUSED) + enum rtx_code index_code ATTRIBUTE_UNUSED, + rtx_insn *insn ATTRIBUTE_UNUSED = NULL) { +#ifdef INSN_BASE_REG_CLASS + return INSN_BASE_REG_CLASS (insn); +#else #ifdef MODE_CODE_BASE_REG_CLASS return MODE_CODE_BASE_REG_CLASS (MACRO_MODE (mode), as, outer_code, index_code); @@ -44,6 +48,7 @@ base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, return BASE_REG_CLASS; #endif #endif +#endif } /* Wrapper function to unify target macros REGNO_MODE_CODE_OK_FOR_BASE_P, @@ -56,8 +61,12 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED, addr_space_t as ATTRIBUTE_UNUSED, enum rtx_code outer_code ATTRIBUTE_UNUSED, - enum rtx_code index_code ATTRIBUTE_UNUSED) + enum rtx_code index_code ATTRIBUTE_UNUSED, + rtx_insn* insn ATTRIBUTE_UNUSED = NULL) { +#ifdef REGNO_OK_FOR_INSN_BASE_P + return REGNO_OK_FOR_INSN_BASE_P (regno, insn); +#else #ifdef REGNO_MODE_CODE_OK_FOR_BASE_P return REGNO_MODE_CODE_OK_FOR_BASE_P (regno, MACRO_MODE (mode), as, outer_code, index_code); @@ -72,6 +81,7 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, return REGNO_OK_FOR_BASE_P (regno); #endif #endif +#endif } /* Wrapper around ok_for_base_p_1, for use after register allocation is @@ -79,12 +89,13 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, inline bool regno_ok_for_base_p (unsigned regno, machine_mode mode, addr_space_t as, - enum rtx_code outer_code, enum rtx_code index_code) + enum rtx_code outer_code, enum rtx_code index_code, + rtx_insn *insn = NULL) { if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) regno = reg_renumber[regno]; - return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); + return ok_for_base_p_1 (regno, mode, as, outer_code, index_code, insn); } #endif /* GCC_ADDRESSES_H */ |