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authorxuli <xuli1@eswincomputing.com>2024-10-23 01:57:51 +0000
committerxuli <xuli1@eswincomputing.com>2024-10-30 00:57:26 +0000
commit179a682d047500604c6612afb425acf481e1a6b2 (patch)
tree7716525ecd648bf7e6b25d685a9d0172ef84c91b /gcc/ada/libgnat/s-maccod.ads
parent4af8db3eca12b2db3753ce4b098cbd0ae32b4796 (diff)
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RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.HEADtrunkmaster
form2: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \ { \ return x >= (T)IMM ? x - (T)IMM : 0; \ } Passed the rv64gcv regression test. Signed-off-by: Li Xu <xuli1@eswincomputing.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_sub_imm-run-5.c: add run case for imm=1. * gcc.target/riscv/sat_u_sub_imm-run-6.c: Ditto. * gcc.target/riscv/sat_u_sub_imm-run-7.c: Ditto. * gcc.target/riscv/sat_u_sub_imm-run-8.c: Ditto. * gcc.target/riscv/sat_u_sub_imm-5_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-6_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-7_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-8_1.c: New test.
Diffstat (limited to 'gcc/ada/libgnat/s-maccod.ads')
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