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| author | mtsamis <manolis.tsamis@vrull.eu> | 2022-08-24 15:22:58 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-11-17 12:59:06 +0100 |
| commit | 705bae2351a870dc3ff59db47fa0de6baaf829c8 (patch) | |
| tree | a1fa191fefe5fa9e0f0469e122f569f4ecb16189 /gcc/ada/lib-xref.ads | |
| parent | 06c8f2ebf062f64e8f4228ec47bdd003df9ef5ed (diff) | |
| download | gcc-705bae2351a870dc3ff59db47fa0de6baaf829c8.zip gcc-705bae2351a870dc3ff59db47fa0de6baaf829c8.tar.gz gcc-705bae2351a870dc3ff59db47fa0de6baaf829c8.tar.bz2 | |
Enable shrink wrapping for the RISC-V target.
This commit implements the target macros (TARGET_SHRINK_WRAP_*) that
enable separate shrink wrapping for function prologues/epilogues in
RISC-V.
Tested against SPEC CPU 2017, this change always has a net-positive
effect on the dynamic instruction count. See the following table for
the breakdown on how this reduces the number of dynamic instructions
per workload on a like-for-like (i.e., same config file; suppressing
shrink-wrapping with -fno-shrink-wrap):
# dynamic instructions
w/o shrink-wrap w/ shrink-wrap reduction
500.perlbench_r 1265716786593 1262156218578 3560568015 0.28%
500.perlbench_r 779224795689 765337009025 13887786664 1.78%
500.perlbench_r 724087331471 711307152522 12780178949 1.77%
502.gcc_r 204259864844 194517006339 9742858505 4.77%
502.gcc_r 244047794302 231555834722 12491959580 5.12%
502.gcc_r 230896069400 221877703011 9018366389 3.91%
502.gcc_r 192130616624 183856450605 8274166019 4.31%
502.gcc_r 258875074079 247756203226 11118870853 4.30%
505.mcf_r 662653430325 660678680547 1974749778 0.30%
520.omnetpp_r 985114167068 934191310154 50922856914 5.17%
523.xalancbmk_r 927037633578 921688937650 5348695928 0.58%
525.x264_r 490953958454 490565583447 388375007 0.08%
525.x264_r 1994662294421 1993171932425 1490361996 0.07%
525.x264_r 1897617120450 1896062750609 1554369841 0.08%
531.deepsjeng_r 1695189878907 1669304130411 25885748496 1.53%
541.leela_r 1925941222222 1897900861198 28040361024 1.46%
548.exchange2_r 2073816227944 2073816226729 1215 0.00%
557.xz_r 379572090003 379057409041 514680962 0.14%
557.xz_r 953117469352 952680431430 437037922 0.05%
557.xz_r 536859579650 536456690164 402889486 0.08%
18421773405376 18223938521833 197834883543 1.07% totals
Signed-off-by: Manolis Tsamis <manolis.tsamis@vrull.eu>
gcc/ChangeLog:
* config/riscv/riscv.cc (struct machine_function): Add array to store
register wrapping information.
(riscv_for_each_saved_reg): Skip registers that are wrapped separetely.
(riscv_get_separate_components): New function.
(riscv_components_for_bb): Likewise.
(riscv_disqualify_components): Likewise.
(riscv_process_components): Likewise.
(riscv_emit_prologue_components): Likewise.
(riscv_emit_epilogue_components): Likewise.
(riscv_set_handled_components): Likewise.
(TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define.
(TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise.
(TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/shrink-wrap-1.c: New test.
Diffstat (limited to 'gcc/ada/lib-xref.ads')
0 files changed, 0 insertions, 0 deletions