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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-05-16 11:01:36 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-05-16 11:01:36 +0000 |
| commit | 3362d76470c5b397b53a699130406f422b83bba7 (patch) | |
| tree | e84132de7f1aaa6bdec02d372ef377a9142f64f4 /gcc/ada/gcc-interface/trans.c | |
| parent | 6232acb724db1be226fc653096ca23201b60b8ee (diff) | |
| download | gcc-3362d76470c5b397b53a699130406f422b83bba7.zip gcc-3362d76470c5b397b53a699130406f422b83bba7.tar.gz gcc-3362d76470c5b397b53a699130406f422b83bba7.tar.bz2 | |
This patch fixes the attributes of integer immediate shifts which were...
This patch fixes the attributes of integer immediate shifts which were
incorrectly modelled as register controlled shifts. Also change EXTR
attribute to being a rotate.
* gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3):
Split integer shifts into shift_reg and bfm.
(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
(ror<mode>3_insn): Likewise.
(<optab>si3_insn_uxtw): Likewise.
(<optab><mode>3_insn): Change to rotate_imm.
(extr<mode>5_insn_alt): Likewise.
(extrsi5_insn_uxtw): Likewise.
(extrsi5_insn_uxtw_alt): Likewise.
From-SVN: r236278
Diffstat (limited to 'gcc/ada/gcc-interface/trans.c')
0 files changed, 0 insertions, 0 deletions