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| author | Sudakshina Das <sudi.das@arm.com> | 2017-12-14 10:35:38 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi@gcc.gnu.org> | 2017-12-14 10:35:38 +0000 |
| commit | 8332c5ee8c5f3bf91eb97666793e9589f2578a05 (patch) | |
| tree | 808154fcd0cba57b6501a2c0282c91e9b488b022 /gcc/ChangeLog | |
| parent | 30af63d7cbde0e47f3b9e3ad2320f7fd65dc762f (diff) | |
| download | gcc-8332c5ee8c5f3bf91eb97666793e9589f2578a05.zip gcc-8332c5ee8c5f3bf91eb97666793e9589f2578a05.tar.gz gcc-8332c5ee8c5f3bf91eb97666793e9589f2578a05.tar.bz2 | |
[PATCH PR81228][AARCH64]Fix ICE by adding LTGT in vec_cmp<mode><v_int_equiv>
This patch is a follow up to the existing discussions on
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01904.html
Bin had earlier submitted this patch to fix the ICE that
occurs because of the missing LTGT in aarch64-simd.md.
That discussion opened up a new bug report PR81647 for
an inconsistent behavior.
As discussed earlier on the gcc-patches discussion and on
the bug report, PR81647 was occurring because of how UNEQ
was handled in aarch64-simd.md rather than LTGT.
Since __builtin_islessgreater is guaranteed to not give an
FP exception but LTGT might, __builtin_islessgreater gets
converted to ~UNEQ very early on in fold_builtin_unordered_cmp.
Thus I will post a separate patch for correcting how UNEQ and
other unordered comparisons are handled in aarch64-simd.md.
This patch is only adding the missing LTGT to plug the ICE.
Testing done: Checked for regressions on bootstrapped
aarch64-none-linux-gnu and added a new compile time test case
that gives out LTGT to make sure it doesn't ICE
*** gcc/ChangeLog ***
2017-12-14 Sudakshina Das <sudi.das@arm.com>
Bin Cheng <bin.cheng@arm.com>
PR target/81228
* config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT
to CCFPEmode.
* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_int_equiv>): Add
LTGT.
*** gcc/testsuite/ChangeLog ***
2017-12-14 Sudakshina Das <sudi.das@arm.com>
PR target/81228
* gcc.dg/pr81228.c: New.
Co-Authored-By: Bin Cheng <bin.cheng@arm.com>
From-SVN: r255625
Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5e18fb9..e33b45f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-12-14 Sudakshina Das <sudi.das@arm.com> + Bin Cheng <bin.cheng@arm.com> + + PR target/81228 + * config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT + to CCFPEmode. + * config/aarch64/aarch64-simd.md (vec_cmp<mode><v_int_equiv>): Add + LTGT. + 2017-12-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64-cores.def (cortex-a55, cortex-a75, |