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| author | John David Anglin <dave.anglin@nrc-cnrc.gc.ca> | 2003-12-20 17:24:15 +0000 |
|---|---|---|
| committer | John David Anglin <danglin@gcc.gnu.org> | 2003-12-20 17:24:15 +0000 |
| commit | 3914c31fc6095844415cef8f73d8efd858765cb7 (patch) | |
| tree | ad63993b40749ecdb0b5c476c3c3a8a3d6c0edf8 /gcc/ChangeLog | |
| parent | 6ae533cf8947fe7f6e536adf5431b13e28f844f3 (diff) | |
| download | gcc-3914c31fc6095844415cef8f73d8efd858765cb7.zip gcc-3914c31fc6095844415cef8f73d8efd858765cb7.tar.gz gcc-3914c31fc6095844415cef8f73d8efd858765cb7.tar.bz2 | |
pa.h (TRAMPOLINE_TEMPLATE): Shorten sequence when generating PA 2.0 code.
* pa.h (TRAMPOLINE_TEMPLATE): Shorten sequence when generating PA
2.0 code.
(TRAMPOLINE_CODE_SIZE, MIN_CACHELINE_SIZE): New defines.
(INITIALIZE_TRAMPOLINE): Rework to pass line length, and aligned start
and end addresses to I and D cache instruction patterns.
* pa.md (anddi3, iordi3): Change predicates of operands 1 and 2 to
and_operand and ior_operand, respectively. When generating 64-bit
code, only one operand needs to be a register operand.
(xordi3): Change predicates of operands 1 and 2 to register_operand.
(one_cmpldi2): Change predicate of operand 1 to register_operand.
(dcacheflush, icacheflush): Revise to flush an arbitrary number of
cache lines.
From-SVN: r74888
Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 955e05f..6e4bac8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2003-12-20 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * pa.h (TRAMPOLINE_TEMPLATE): Shorten sequence when generating PA + 2.0 code. + (TRAMPOLINE_CODE_SIZE, MIN_CACHELINE_SIZE): New defines. + (INITIALIZE_TRAMPOLINE): Rework to pass line length, and aligned start + and end addresses to I and D cache instruction patterns. + * pa.md (anddi3, iordi3): Change predicates of operands 1 and 2 to + and_operand and ior_operand, respectively. When generating 64-bit + code, only one operand needs to be a register operand. + (xordi3): Change predicates of operands 1 and 2 to register_operand. + (one_cmpldi2): Change predicate of operand 1 to register_operand. + (dcacheflush, icacheflush): Revise to flush an arbitrary number of + cache lines. + 2003-12-20 Josef Zlomek <zlomekj@suse.cz> PR optimization/13430, PR optimization/12322 |