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| author | Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> | 2022-06-14 12:39:49 +0900 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-06-15 16:55:36 -0700 |
| commit | cfad4856fa46abc878934a9433d0bfc2482ccf00 (patch) | |
| tree | cb637df127a7f8a5cc60b7618c34921650db7411 /fixincludes | |
| parent | c95e307e3a978166cd5d6817ec9d8293825ff3fb (diff) | |
| download | gcc-cfad4856fa46abc878934a9433d0bfc2482ccf00.zip gcc-cfad4856fa46abc878934a9433d0bfc2482ccf00.tar.gz gcc-cfad4856fa46abc878934a9433d0bfc2482ccf00.tar.bz2 | |
xtensa: Eliminate unwanted reg-reg moves during DFmode input reloads
When spilled DFmode registers are reloaded in, once loaded into a pair of
SImode regs and then copied from that regs. Such unwanted reg-reg moves
seems not to be eliminated at the "cprop_hardreg" stage, despite no problem
in output reloads.
Luckily it is easy to resolve such inefficiencies, with the use of peephole2
pattern.
gcc/ChangeLog:
* config/xtensa/predicates.md (reload_operand):
New predicate.
* config/xtensa/xtensa.md: New peephole2 pattern.
Diffstat (limited to 'fixincludes')
0 files changed, 0 insertions, 0 deletions