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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-11-22 10:56:13 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-11-22 10:56:13 +0000 |
| commit | aa5521f298fc8042e11e7b352270a33e6c454cb4 (patch) | |
| tree | c072a153eaf0109b9236845c6a750234913a9aee /depcomp | |
| parent | 27071013521b015d17a2666448f27a6ff0c55aca (diff) | |
| download | gcc-aa5521f298fc8042e11e7b352270a33e6c454cb4.zip gcc-aa5521f298fc8042e11e7b352270a33e6c454cb4.tar.gz gcc-aa5521f298fc8042e11e7b352270a33e6c454cb4.tar.bz2 | |
Fix markup in gcc.dg/vect/vect-cond-reduc-3.c
gcc.dg/vect/vect-cond-reduc-3.c had been failing on
arm-linux-gnueabihf since the test was added, because the test needs
support for VEC_COND_EXPR <float cmp float, int, int> whereas the target
only supports VEC_COND_EXPRs in which all modes are the same. (I have
a fix for that, but it's not really stage 3 material.)
2019-11-22 Richard Sandiford <richard.sandiford@arm.com>
gcc/testsuite/
* gcc.dg/vect/vect-cond-reduc-3.c: Require vect_cond_mixed
rather than vect_condition.
From-SVN: r278612
Diffstat (limited to 'depcomp')
0 files changed, 0 insertions, 0 deletions