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authorPan Li <pan2.li@intel.com>2023-08-29 18:41:30 +0800
committerPan Li <pan2.li@intel.com>2023-08-29 22:09:45 +0800
commitd16af3ebea84749ac673db29a4124d2dc7cd369e (patch)
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parentf30d6a48635b5b180e46c51138d0938d33abd942 (diff)
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RISC-V: Fix one ICE for vect test vect-multitypes-5
There will be one ICE when build vect-multitypes-5.c similar as below: riscv64-unknown-elf-gcc -O3 \ -march=rv64imafdcv -mabi=lp64d -mcmodel=medlow \ -fdiagnostics-plain-output -flto -ffat-lto-objects \ --param riscv-autovec-preference=scalable -Wno-psabi \ -ftree-vectorize -fno-tree-loop-distribute-patterns \ -fno-vect-cost-model -fno-common -O2 -fdump-tree-vect-details \ gcc/testsuite/gcc.dg/vect/vect-multitypes-5.c -o test.elf -lm The below RTL is not well handled in riscv_legitimize_const_move, and then fall through to the default pass. Then the default force_const_mem will NULL_RTX, and will have ICE when operating one the NULL_RTX. (const:DI (plus:DI (symbol_ref:DI ("ic") [flags 0x2] <var_decl 0x7fe57740be10 ic>) (const_poly_int:DI [16, 16]))) This patch would like to take care of this rtl in riscv_legitimize_const_move. Signed-off-by: Pan Li <pan2.li@intel.com> Co-Authored-By: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_poly_move): New declaration. (riscv_legitimize_const_move): Handle ref plus const poly.
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