RISC-V: Enable movmisalign for VLS modes

Prevous patch (which removed VLA modes movmisalign pattern) to fix run-time bug.
Such patch disable vectorization for misalign data movement.

After I check LLVM codes, LLVM supports misalign for VLS modes.

Before this patch:

sll     a5,a4,0x1
add     a5,a5,a1
lhu     a3,64(a5)
lbu     a5,66(a5)
addw    a4,a4,1
srl     a3,a3,0x8
sll     a5,a5,0x8
or      a5,a5,a3
sh      a5,0(a2)
add     a2,a2,2
bne     a4,a0,101f8 <foo+0x14>

After this patch:

foo:
	lui	a0,%hi(.LANCHOR0)
	addi	a0,a0,%lo(.LANCHOR0)
	addi	sp,sp,-16
	addi	a1,a0,1
	li	a2,64
	sd	ra,8(sp)
	vsetvli	zero,a2,e8,m4,ta,ma
	addi	a0,a0,128
	vle8.v	v4,0(a1)
	vse8.v	v4,0(a0)
	call	memcmp
	bne	a0,zero,.L6
	ld	ra,8(sp)
	addi	sp,sp,16
	jr	ra
.L6:
	call	abort

Note this patch has passed all testcases in "vect" which are related to alignment.

gcc/ChangeLog:

	* config/riscv/autovec-vls.md (movmisalign<mode>): New pattern.
	* config/riscv/riscv.cc (riscv_support_vector_misalignment): Support
	VLS misalign.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/misalign-1.c: New test.

0 files changed, 0 insertions, 0 deletions