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| author | Xi Ruoyao <xry111@xry111.site> | 2025-03-07 12:49:54 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2025-03-10 17:12:05 +0800 |
| commit | c7d493baf13f1f144f2c4bc375383b6ce5d88a76 (patch) | |
| tree | a8b35640d4434608ca0338cac0a485013978937f /contrib/gcc-changelog/git_commit.py | |
| parent | 9fe5106ea92218380ea2a7166417565f79fe680d (diff) | |
| download | gcc-c7d493baf13f1f144f2c4bc375383b6ce5d88a76.zip gcc-c7d493baf13f1f144f2c4bc375383b6ce5d88a76.tar.gz gcc-c7d493baf13f1f144f2c4bc375383b6ce5d88a76.tar.bz2 | |
LoongArch: Fix ICE when trying to recognize bitwise + alsl.w pair [PR119127]
When we call loongarch_reassoc_shift_bitwise for
<optab>_alsl_reversesi_extend, the mask is in DImode but we are trying
to operate it in SImode, causing an ICE.
To fix the issue sign-extend the mask into the mode we want. And also
specially handle the case the mask is extended into -1 to avoid a
miss-optimization.
gcc/ChangeLog:
PR target/119127
* config/loongarch/loongarch.cc
(loongarch_reassoc_shift_bitwise): Sign extend mask to mode,
specially handle the case it's extended to -1.
* config/loongarch/loongarch.md
(loongarch_reassoc_shift_bitwise): Update the comment for the
special case.
Diffstat (limited to 'contrib/gcc-changelog/git_commit.py')
0 files changed, 0 insertions, 0 deletions