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| author | Lulu Cheng <chenglulu@loongson.cn> | 2025-05-25 11:15:07 +0800 |
|---|---|---|
| committer | Lulu Cheng <chenglulu@loongson.cn> | 2025-11-03 10:09:09 +0800 |
| commit | abb22d046d3ee0b6a6ae2922bdd354e65096d8ca (patch) | |
| tree | a893f8f2d74362bc43b34260174225e6b5c2d52d /contrib/gcc-changelog/git_commit.py | |
| parent | f59cabadd0b678d744ba1f185ad215f561378a4e (diff) | |
| download | gcc-abb22d046d3ee0b6a6ae2922bdd354e65096d8ca.zip gcc-abb22d046d3ee0b6a6ae2922bdd354e65096d8ca.tar.gz gcc-abb22d046d3ee0b6a6ae2922bdd354e65096d8ca.tar.bz2 | |
LoongArch: Optimize normal immediate data loading.
Ensure that only one register is used when loading immediate values.
The original immediate value load is handled through virtual
registers, resulting in the following load operation
(0x1234567890abcdef):
lu12i.w $r4,-456004 # 0xfffffffffff90abc
or $r12,$r0,$r0
ori $r4,$r4,3567
lu32i.d $r12,0x45678
lu32i.d $r4,0
or $r4,$r4,$r12
lu52i.d $r4,$r4,0x123
The optimized sequence is as follows:
lu12i.w $r4,-456004 # 0xfffffffffff90abc
ori $r4,$r4,3567
lu32i.d $r4,0x45678
lu52i.d $r4,$r4,0x123
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_move_integer):
No new virtual register is allocated during immediate load.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/imm-load.c: Modify.
Diffstat (limited to 'contrib/gcc-changelog/git_commit.py')
0 files changed, 0 insertions, 0 deletions