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| author | zhongjuzhe <juzhe.zhong@rivai.ai> | 2022-08-30 14:27:52 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-09-01 10:01:54 +0800 |
| commit | e8c83ab9d5142a305bbd75c7ff0e41eae38433df (patch) | |
| tree | 691a0eb211372248a618fe4f27577003c58b80fd /README | |
| parent | 8fe75147a948ceab6fb9afbe0ee698517ce1dda0 (diff) | |
| download | gcc-e8c83ab9d5142a305bbd75c7ff0e41eae38433df.zip gcc-e8c83ab9d5142a305bbd75c7ff0e41eae38433df.tar.gz gcc-e8c83ab9d5142a305bbd75c7ff0e41eae38433df.tar.bz2 | |
RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector
registers.
Diffstat (limited to 'README')
0 files changed, 0 insertions, 0 deletions