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| author | Edwin Lu <ewlu@rivosinc.com> | 2023-09-12 09:31:40 -0700 |
|---|---|---|
| committer | Edwin Lu <ewlu@rivosinc.com> | 2023-09-12 09:31:40 -0700 |
| commit | 360c8cad6a727d5afd43017ca1ce9a84c6db61c5 (patch) | |
| tree | a9ba82eeac211d50f07a74cd33cd5a90d760d838 /MAINTAINERS | |
| parent | 52f65d17c85fa513887a3bb31e3c3c329d9ace58 (diff) | |
| download | gcc-360c8cad6a727d5afd43017ca1ce9a84c6db61c5.zip gcc-360c8cad6a727d5afd43017ca1ce9a84c6db61c5.tar.gz gcc-360c8cad6a727d5afd43017ca1ce9a84c6db61c5.tar.bz2 | |
RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert
Updates autovec instruction that was added after last patch and turns on the
assert statement to ensure all new instructions have a type.
* config/riscv/autovec-opt.md: Update type
* config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions