diff options
author | Kewen Lin <linkw@linux.ibm.com> | 2023-06-12 01:08:22 -0500 |
---|---|---|
committer | Kewen Lin <linkw@linux.ibm.com> | 2023-06-12 01:08:22 -0500 |
commit | ff83d1b47aadcdaf80a4fda84b0dc00bb2cd3641 (patch) | |
tree | 36d71b8548fc6ede59e83ed5d52ec1f602b46553 | |
parent | 388809f2afde874180da0669c669e241037eeba0 (diff) | |
download | gcc-ff83d1b47aadcdaf80a4fda84b0dc00bb2cd3641.zip gcc-ff83d1b47aadcdaf80a4fda84b0dc00bb2cd3641.tar.gz gcc-ff83d1b47aadcdaf80a4fda84b0dc00bb2cd3641.tar.bz2 |
rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]
As PR109932 shows, builtins __builtin_{un,}pack_vector_int128
should be guarded under vsx rather than power7, as their
corresponding bif patterns have the conditions TARGET_VSX
and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode). This patch is to
move __builtin_{un,}pack_vector_int128 to stanza vsx to ensure
their supports.
PR target/109932
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
__builtin_unpack_vector_int128): Move from stanza power7 to vsx.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr109932-1.c: New test.
* gcc.target/powerpc/pr109932-2.c: New test.
-rw-r--r-- | gcc/config/rs6000/rs6000-builtins.def | 14 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr109932-1.c | 16 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr109932-2.c | 16 |
3 files changed, 39 insertions, 7 deletions
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 289a379..5ac6af4 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -2009,6 +2009,13 @@ const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>); XXSPLTD_V2DI vsx_xxspltd_v2di {} + const vsq __builtin_pack_vector_int128 (unsigned long long, \ + unsigned long long); + PACK_V1TI packv1ti {} + + const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); + UNPACK_V1TI unpackv1ti {} + ; Power7 builtins (ISA 2.06). [power7] @@ -2030,16 +2037,9 @@ const unsigned int __builtin_divweu (unsigned int, unsigned int); DIVWEU diveu_si {} - const vsq __builtin_pack_vector_int128 (unsigned long long, \ - unsigned long long); - PACK_V1TI packv1ti {} - void __builtin_ppc_speculation_barrier (); SPECBARR speculation_barrier {} - const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); - UNPACK_V1TI unpackv1ti {} - ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing). [power7-64] diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c new file mode 100644 index 0000000..3e3f9ea --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx" } */ + +/* Verify there is no ICE but one expected error message instead. */ + +#include <altivec.h> + +extern vector signed __int128 res_vslll; +extern unsigned long long aull[2]; + +void +testVectorInt128Pack () +{ + res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c new file mode 100644 index 0000000..3e3f9ea --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx" } */ + +/* Verify there is no ICE but one expected error message instead. */ + +#include <altivec.h> + +extern vector signed __int128 res_vslll; +extern unsigned long long aull[2]; + +void +testVectorInt128Pack () +{ + res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */ +} + |