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| author | Bernd Edlinger <bernd.edlinger@hotmail.de> | 2016-01-01 18:45:41 +0000 |
|---|---|---|
| committer | Bernd Edlinger <edlinger@gcc.gnu.org> | 2016-01-01 18:45:41 +0000 |
| commit | fecd16d2387f1f1b0f376aba290171c880897ab0 (patch) | |
| tree | 48db2ab9dc8c20e9a7d3b8b661d671d57c1c2d9b | |
| parent | 2f9686033d9d358b082da38c1b8a9380dfa9b961 (diff) | |
| download | gcc-fecd16d2387f1f1b0f376aba290171c880897ab0.zip gcc-fecd16d2387f1f1b0f376aba290171c880897ab0.tar.gz gcc-fecd16d2387f1f1b0f376aba290171c880897ab0.tar.bz2 | |
re PR target/68917 (test suite failure for builtin-bitops-1.c)
PR target/68917
* config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of
SI values. Explicitly convert SI to DI and vice-versa.
From-SVN: r232028
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/tilegx/tilegx.md | 11 |
2 files changed, 13 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d27a83..8b1fd2d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-01-01 Bernd Edlinger <bernd.edlinger@hotmail.de> + + PR target/68917 + * config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of + SI values. Explicitly convert SI to DI and vice-versa. + 2016-01-01 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/69070 diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 944953c..a2c1aef 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -1799,13 +1799,16 @@ (define_expand "clzsi2" [(set (match_dup 2) - (ashift:DI (match_operand:SI 1 "reg_or_0_operand" "") + (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))) + (set (match_dup 2) + (ashift:DI (match_dup 2) (const_int 32))) - (set (subreg:DI (match_operand:SI 0 "register_operand" "") 0) - (clz:DI (match_dup 2)))] + (set (match_dup 2) + (clz:DI (match_dup 2))) + (set (match_operand:SI 0 "register_operand" "") + (subreg:SI (match_dup 2) 0))] "" { - operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0); operands[2] = gen_reg_rtx (DImode); }) |