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author | Wei Mi <wmi@google.com> | 2013-11-04 21:31:07 +0000 |
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committer | Wei Mi <wmi@gcc.gnu.org> | 2013-11-04 21:31:07 +0000 |
commit | fd5564d3c71195714c28ba150de7e9b90bf9c83d (patch) | |
tree | 514dde8de45ba210fcf4eb75cdacf533f175728b | |
parent | 8cfa63d2237082e84f78cc855614475a78f18c13 (diff) | |
download | gcc-fd5564d3c71195714c28ba150de7e9b90bf9c83d.zip gcc-fd5564d3c71195714c28ba150de7e9b90bf9c83d.tar.gz gcc-fd5564d3c71195714c28ba150de7e9b90bf9c83d.tar.bz2 |
i386-c.c (ix86_target_macros_internal): Separate PROCESSOR_COREI7_AVX out from PROCESSOR_COREI7.
2013-11-04 Wei Mi <wmi@google.com>
* gcc/config/i386/i386-c.c (ix86_target_macros_internal): Separate
PROCESSOR_COREI7_AVX out from PROCESSOR_COREI7.
* gcc/config/i386/i386.c (ix86_option_override_internal): Ditto.
(ix86_issue_rate): Ditto.
(ix86_adjust_cost): Ditto.
(ia32_multipass_dfa_lookahead): Ditto.
(ix86_sched_init_global): Ditto.
(get_builtin_code_for_version): Ditto.
* gcc/config/i386/i386.h (enum target_cpu_default): Ditto.
(enum processor_type): Ditto.
* gcc/config/i386/x86-tune.def (DEF_TUNE): Ditto.
From-SVN: r204367
-rw-r--r-- | gcc/ChangeLog | 14 | ||||
-rw-r--r-- | gcc/config/i386/i386-c.c | 7 | ||||
-rw-r--r-- | gcc/config/i386/i386.c | 18 | ||||
-rw-r--r-- | gcc/config/i386/i386.h | 3 | ||||
-rw-r--r-- | gcc/config/i386/x86-tune.def | 4 |
5 files changed, 41 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 18db887..f858406 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2013-11-04 Wei Mi <wmi@google.com> + + * gcc/config/i386/i386-c.c (ix86_target_macros_internal): Separate + PROCESSOR_COREI7_AVX out from PROCESSOR_COREI7. + * gcc/config/i386/i386.c (ix86_option_override_internal): Ditto. + (ix86_issue_rate): Ditto. + (ix86_adjust_cost): Ditto. + (ia32_multipass_dfa_lookahead): Ditto. + (ix86_sched_init_global): Ditto. + (get_builtin_code_for_version): Ditto. + * gcc/config/i386/i386.h (enum target_cpu_default): Ditto. + (enum processor_type): Ditto. + * gcc/config/i386/x86-tune.def (DEF_TUNE): Ditto. + 2013-11-04 Vladimir Makarov <vmakarov@redhat.com> PR rtl-optimization/58967 diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index a6eaf8a..690169d 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -141,6 +141,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__corei7"); def_or_undef (parse_in, "__corei7__"); break; + case PROCESSOR_COREI7_AVX: + def_or_undef (parse_in, "__corei7_avx"); + def_or_undef (parse_in, "__corei7_avx__"); + break; case PROCESSOR_HASWELL: def_or_undef (parse_in, "__core_avx2"); def_or_undef (parse_in, "__core_avx2__"); @@ -238,6 +242,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_COREI7: def_or_undef (parse_in, "__tune_corei7__"); break; + case PROCESSOR_COREI7_AVX: + def_or_undef (parse_in, "__tune_corei7_avx__"); + break; case PROCESSOR_HASWELL: def_or_undef (parse_in, "__tune_core_avx2__"); break; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 902e169..631f3b9 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1833,8 +1833,9 @@ const struct processor_costs *ix86_cost = &pentium_cost; #define m_P4_NOCONA (m_PENT4 | m_NOCONA) #define m_CORE2 (1<<PROCESSOR_CORE2) #define m_COREI7 (1<<PROCESSOR_COREI7) +#define m_COREI7_AVX (1<<PROCESSOR_COREI7_AVX) #define m_HASWELL (1<<PROCESSOR_HASWELL) -#define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL) +#define m_CORE_ALL (m_CORE2 | m_COREI7 | m_COREI7_AVX | m_HASWELL) #define m_ATOM (1<<PROCESSOR_ATOM) #define m_SLM (1<<PROCESSOR_SLM) @@ -2299,6 +2300,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] = {&core_cost, 16, 10, 16, 10, 16}, /* Core i7 */ {&core_cost, 16, 10, 16, 10, 16}, + /* Core i7 avx */ + {&core_cost, 16, 10, 16, 10, 16}, /* Core avx2 */ {&core_cost, 16, 10, 16, 10, 16}, {&generic_cost, 16, 10, 16, 10, 16}, @@ -2328,6 +2331,7 @@ static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = "nocona", "core2", "corei7", + "corei7-avx", "core-avx2", "atom", "slm", @@ -3016,12 +3020,12 @@ ix86_option_override_internal (bool main_args_p, {"corei7", PROCESSOR_COREI7, CPU_COREI7, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR}, - {"corei7-avx", PROCESSOR_COREI7, CPU_COREI7, + {"corei7-avx", PROCESSOR_COREI7_AVX, CPU_COREI7, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, - {"core-avx-i", PROCESSOR_COREI7, CPU_COREI7, + {"core-avx-i", PROCESSOR_COREI7_AVX, CPU_COREI7, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE @@ -24807,6 +24811,7 @@ ix86_issue_rate (void) case PROCESSOR_CORE2: case PROCESSOR_COREI7: + case PROCESSOR_COREI7_AVX: case PROCESSOR_HASWELL: return 4; @@ -25103,6 +25108,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) case PROCESSOR_CORE2: case PROCESSOR_COREI7: + case PROCESSOR_COREI7_AVX: case PROCESSOR_HASWELL: memory = get_attr_memory (insn); @@ -25181,6 +25187,7 @@ ia32_multipass_dfa_lookahead (void) case PROCESSOR_CORE2: case PROCESSOR_COREI7: + case PROCESSOR_COREI7_AVX: case PROCESSOR_HASWELL: case PROCESSOR_ATOM: case PROCESSOR_SLM: @@ -25821,6 +25828,7 @@ ix86_sched_init_global (FILE *dump ATTRIBUTE_UNUSED, { case PROCESSOR_CORE2: case PROCESSOR_COREI7: + case PROCESSOR_COREI7_AVX: case PROCESSOR_HASWELL: /* Do not perform multipass scheduling for pre-reload schedule to save compile time. */ @@ -29672,6 +29680,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) arg_str = "corei7"; priority = P_PROC_SSE4_2; break; + case PROCESSOR_COREI7_AVX: + arg_str = "corei7-avx"; + priority = P_PROC_SSE4_2; + break; case PROCESSOR_ATOM: arg_str = "atom"; priority = P_PROC_SSSE3; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index c979ee5..f07fd79 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -304,6 +304,7 @@ extern const struct processor_costs ix86_size_cost; #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) #define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7) +#define TARGET_COREI7_AVX (ix86_tune == PROCESSOR_COREI7_AVX) #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) @@ -613,6 +614,7 @@ enum target_cpu_default TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_core2, TARGET_CPU_DEFAULT_corei7, + TARGET_CPU_DEFAULT_corei7_avx, TARGET_CPU_DEFAULT_haswell, TARGET_CPU_DEFAULT_atom, TARGET_CPU_DEFAULT_slm, @@ -2229,6 +2231,7 @@ enum processor_type PROCESSOR_NOCONA, PROCESSOR_CORE2, PROCESSOR_COREI7, + PROCESSOR_COREI7_AVX, PROCESSOR_HASWELL, PROCESSOR_GENERIC, PROCESSOR_AMDFAM10, diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 6e5d2fe..93977a9 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -300,12 +300,12 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", - m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC) + m_COREI7 | m_COREI7_AVX | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC) /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", - m_COREI7 | m_BDVER | m_SLM | m_GENERIC) + m_COREI7 | m_COREI7_AVX | m_BDVER | m_SLM | m_GENERIC) /* Use packed single precision instructions where posisble. I.e. movups instead of movupd. */ |