AArch64: update testsuite to account for new zero moves

The patch series will adjust how zeros are created.  In principal it doesn't
matter the exact lane size a zero gets created on but this makes the tests a
bit fragile.

This preparation patch will update the testsuite to accept multiple variants
of ways to create vector zeros to accept both the current syntax and the one
being transitioned to in the series.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/ldp_stp_18.c: Update zero regexpr.
	* gcc.target/aarch64/memset-corner-cases.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_bf16.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_f16.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_f32.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_f64.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_s16.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_s32.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_s64.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_s8.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_u16.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_u32.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_u64.c: Likewise.
	* gcc.target/aarch64/sme/acle-asm/revd_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acge_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acge_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acge_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acgt_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acgt_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acgt_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acle_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acle_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/acle_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/aclt_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/aclt_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/aclt_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/bic_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/bic_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_u8.c: Likewise.
	* gcc.target/aarch64/sve/const_fold_div_1.c: Likewise.
	* gcc.target/aarch64/sve/const_fold_mul_1.c: Likewise.
	* gcc.target/aarch64/sve/dup_imm_1.c: Likewise.
	* gcc.target/aarch64/sve/fdup_1.c: Likewise.
	* gcc.target/aarch64/sve/fold_div_zero.c: Likewise.
	* gcc.target/aarch64/sve/fold_mul_zero.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_2.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_3.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_4.c: Likewise.
	* gcc.target/aarch64/vect-fmovd-zero.c: Likewise.

52 files changed, 410 insertions, 412 deletions

diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c
index eaa855c..ea9fffc 100644
--- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c
+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c
@@ -15,7 +15,7 @@ CONST_FN (4, double, 0);
 
 /*
 ** const_8_double_0:
-**	movi	v([0-9]+)\.2d, .*
+**	movi	v([0-9]+)\.\d+[bhsd], .*
 **	stp	q\1, q\1, \[x0\]
 **	stp	q\1, q\1, \[x0, #?32\]
 **	ret
diff --git a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
index d4c7527..0b12c88 100644
--- a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
+++ b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
@@ -29,7 +29,7 @@ set0byte (int64_t *src)
 
 /* 35bytes would become 4 scalar instructions.  So favour NEON.
 **set0neon:
-**	movi	v([0-9]+).4s, 0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	stp	q\1, q\1, \[x0\]
 **	str	wzr, \[x0, 31\]
 **	ret
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c
index 6507c5a..c8f0dc5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_bf16_z_tied1, svbfloat16_t,
 
 /*
 ** revd_bf16_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c
index 1a2f893..a02e2d4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_f16_z_tied1, svfloat16_t,
 
 /*
 ** revd_f16_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c
index 81c77d5..28cdba5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_f32_z_tied1, svfloat32_t,
 
 /*
 ** revd_f32_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c
index fce6d65..3f949b8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_f64_z_tied1, svfloat64_t,
 
 /*
 ** revd_f64_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c
index a2eba6a..621ae02 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s16_z_tied1, svint16_t,
 
 /*
 ** revd_s16_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c
index cbc0dc0..d388108 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s32_z_tied1, svint32_t,
 
 /*
 ** revd_s32_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c
index aa963d3..f5dbbaa 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s64_z_tied1, svint64_t,
 
 /*
 ** revd_s64_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c
index 4291b71..663cd41 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s8_z_tied1, svint8_t,
 
 /*
 ** revd_s8_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c
index eaed0d1..83a414d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u16_z_tied1, svuint16_t,
 
 /*
 ** revd_u16_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c
index 3b76c70..5ba00cb 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u32_z_tied1, svuint32_t,
 
 /*
 ** revd_u32_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c
index 4589c46..0c016c7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u64_z_tied1, svuint64_t,
 
 /*
 ** revd_u64_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c
index ac5d749..b9f5935 100644
--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c
@@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u8_z_tied1, svuint8_t,
 
 /*
 ** revd_u8_z_untied:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	revd	z0\.q, p0/m, z1\.q
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c
index acef173..747b317 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c
@@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acge_h4_f16, svfloat16_t, float16_t,
 
 /*
 ** acge_0_f16:
-**	mov	(z[0-9]+\.h), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
-**	facge	p0\.h, p1/z, z0\.h, \1
+**	facge	p0\.h, p1/z, z0\.h, z\1\.h
 ** |
 **	facle	p0\.h, p1/z, \1, z0\.h
 ** )
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c
index c3d195ab..5bc5a35 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c
@@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acge_s4_f32, svfloat32_t, float32_t,
 
 /*
 ** acge_0_f32:
-**	mov	(z[0-9]+\.s), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
-**	facge	p0\.s, p1/z, z0\.s, \1
+**	facge	p0\.s, p1/z, z0\.s, z\1\.s
 ** |
 **	facle	p0\.s, p1/z, \1, z0\.s
 ** )
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c
index 207ce93..a51ec69 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c
@@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acge_d4_f64, svfloat64_t, float64_t,
 
 /*
 ** acge_0_f64:
-**	mov	(z[0-9]+\.d), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
-**	facge	p0\.d, p1/z, z0\.d, \1
+**	facge	p0\.d, p1/z, z0\.d, z\1\.d
 ** |
 **	facle	p0\.d, p1/z, \1, z0\.d
 ** )
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c
index 53c6335..9844dfa 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c
@@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acgt_h4_f16, svfloat16_t, float16_t,
 
 /*
 ** acgt_0_f16:
-**	mov	(z[0-9]+\.h), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
-**	facgt	p0\.h, p1/z, z0\.h, \1
+**	facgt	p0\.h, p1/z, z0\.h, z\1\.h
 ** |
 **	faclt	p0\.h, p1/z, \1, z0\.h
 ** )
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c
index d71c84e..a1ce64d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c
@@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acgt_s4_f32, svfloat32_t, float32_t,
 
 /*
 ** acgt_0_f32:
-**	mov	(z[0-9]+\.s), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
-**	facgt	p0\.s, p1/z, z0\.s, \1
+**	facgt	p0\.s, p1/z, z0\.s, z\1\.s
 ** |
 **	faclt	p0\.s, p1/z, \1, z0\.s
 ** )
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c
index 15d549e..430dc34 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c
@@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acgt_d4_f64, svfloat64_t, float64_t,
 
 /*
 ** acgt_0_f64:
-**	mov	(z[0-9]+\.d), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
-**	facgt	p0\.d, p1/z, z0\.d, \1
+**	facgt	p0\.d, p1/z, z0\.d, z\1\.d
 ** |
 **	faclt	p0\.d, p1/z, \1, z0\.d
 ** )
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c
index ed6721d..8e15f26 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c
@@ -44,11 +44,11 @@ TEST_COMPARE_ZD (acle_h4_f16, svfloat16_t, float16_t,
 
 /*
 ** acle_0_f16:
-**	mov	(z[0-9]+\.h), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
 **	facge	p0\.h, p1/z, \1, z0\.h
 ** |
-**	facle	p0\.h, p1/z, z0\.h, \1
+**	facle	p0\.h, p1/z, z0\.h, z\1\.h
 ** )
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c
index 7fc9da7..21368a6 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c
@@ -44,11 +44,11 @@ TEST_COMPARE_ZD (acle_s4_f32, svfloat32_t, float32_t,
 
 /*
 ** acle_0_f32:
-**	mov	(z[0-9]+\.s), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
 **	facge	p0\.s, p1/z, \1, z0\.s
 ** |
-**	facle	p0\.s, p1/z, z0\.s, \1
+**	facle	p0\.s, p1/z, z0\.s, z\1\.s
 ** )
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c
index ecbb8e5..26d096f 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c
@@ -44,11 +44,11 @@ TEST_COMPARE_ZD (acle_d4_f64, svfloat64_t, float64_t,
 
 /*
 ** acle_0_f64:
-**	mov	(z[0-9]+\.d), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
 **	facge	p0\.d, p1/z, \1, z0\.d
 ** |
-**	facle	p0\.d, p1/z, z0\.d, \1
+**	facle	p0\.d, p1/z, z0\.d, z\1\.d
 ** )
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c
index e5f5040..f313e5d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c
@@ -44,11 +44,11 @@ TEST_COMPARE_ZD (aclt_h4_f16, svfloat16_t, float16_t,
 
 /*
 ** aclt_0_f16:
-**	mov	(z[0-9]+\.h), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
 **	facgt	p0\.h, p1/z, \1, z0\.h
 ** |
-**	faclt	p0\.h, p1/z, z0\.h, \1
+**	faclt	p0\.h, p1/z, z0\.h, z\1\.h
 ** )
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c
index f408264..f2bc5dc 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c
@@ -44,11 +44,11 @@ TEST_COMPARE_ZD (aclt_s4_f32, svfloat32_t, float32_t,
 
 /*
 ** aclt_0_f32:
-**	mov	(z[0-9]+\.s), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
 **	facgt	p0\.s, p1/z, \1, z0\.s
 ** |
-**	faclt	p0\.s, p1/z, z0\.s, \1
+**	faclt	p0\.s, p1/z, z0\.s, z\1\.s
 ** )
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c
index 0170b33..03384b0 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c
@@ -44,11 +44,11 @@ TEST_COMPARE_ZD (aclt_d4_f64, svfloat64_t, float64_t,
 
 /*
 ** aclt_0_f64:
-**	mov	(z[0-9]+\.d), #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 ** (
 **	facgt	p0\.d, p1/z, \1, z0\.d
 ** |
-**	faclt	p0\.d, p1/z, z0\.d, \1
+**	faclt	p0\.d, p1/z, z0\.d, z\1\.d
 ** )
 **	ret
 */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c
index d1ffefa..75bc26c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c
@@ -250,7 +250,7 @@ TEST_UNIFORM_Z (bic_128_s8_x, svint8_t,
 
 /*
 ** bic_255_s8_x:
-**	mov	z0\.b, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (bic_255_s8_x, svint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c
index b7528ce..83089d4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c
@@ -250,7 +250,7 @@ TEST_UNIFORM_Z (bic_128_u8_x, svuint8_t,
 
 /*
 ** bic_255_u8_x:
-**	mov	z0\.b, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (bic_255_u8_x, svuint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c
index 8f702cd..21a9454 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c
@@ -32,8 +32,8 @@ TEST_COMPARE_ZD (cmpuo_h4_f16, svfloat16_t, float16_t,
 
 /*
 ** cmpuo_0_f16:
-**	mov	(z[0-9]+\.h), #0
-**	fcmuo	p0\.h, p1/z, (z0\.h, \1|\1, z0\.h)
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	fcmuo	p0\.h, p1/z, (z0\.h, z\1\.h|z\1\.h, z0\.h)
 **	ret
 */
 TEST_COMPARE_Z (cmpuo_0_f16, svfloat16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c
index 8827604..db4093d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c
@@ -32,8 +32,8 @@ TEST_COMPARE_ZD (cmpuo_s4_f32, svfloat32_t, float32_t,
 
 /*
 ** cmpuo_0_f32:
-**	mov	(z[0-9]+\.s), #0
-**	fcmuo	p0\.s, p1/z, (z0\.s, \1|\1, z0\.s)
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	fcmuo	p0\.s, p1/z, (z0\.s, z\1\.s|z\1\.s, z0\.s)
 **	ret
 */
 TEST_COMPARE_Z (cmpuo_0_f32, svfloat32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c
index d7a71ec..9fff531 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c
@@ -32,8 +32,8 @@ TEST_COMPARE_ZD (cmpuo_d4_f64, svfloat64_t, float64_t,
 
 /*
 ** cmpuo_0_f64:
-**	mov	(z[0-9]+\.d), #0
-**	fcmuo	p0\.d, p1/z, (z0\.d, \1|\1, z0\.d)
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	fcmuo	p0\.d, p1/z, (z0\.d, z\1\.d|z\1\.d, z0\.d)
 **	ret
 */
 TEST_COMPARE_Z (cmpuo_0_f64, svfloat64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c
index a90c711..68e41ab 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c
@@ -13,7 +13,7 @@ TEST_UNIFORM_Z (dup_1_f16, svfloat16_t,
 
 /*
 ** dup_0_f16:
-**	mov	z0\.h, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f16, svfloat16_t,
@@ -120,7 +120,7 @@ TEST_UNIFORM_Z (dup_1_f16_z, svfloat16_t,
 
 /*
 ** dup_0_f16_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f16_z, svfloat16_t,
@@ -170,7 +170,7 @@ TEST_UNIFORM_Z (dup_1_f16_x, svfloat16_t,
 
 /*
 ** dup_0_f16_x:
-**	mov	z0\.h, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f16_x, svfloat16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c
index ba23781..29f4e52 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c
@@ -13,7 +13,7 @@ TEST_UNIFORM_Z (dup_1_f32, svfloat32_t,
 
 /*
 ** dup_0_f32:
-**	mov	z0\.s, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f32, svfloat32_t,
@@ -118,7 +118,7 @@ TEST_UNIFORM_Z (dup_1_f32_z, svfloat32_t,
 
 /*
 ** dup_0_f32_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f32_z, svfloat32_t,
@@ -166,7 +166,7 @@ TEST_UNIFORM_Z (dup_1_f32_x, svfloat32_t,
 
 /*
 ** dup_0_f32_x:
-**	mov	z0\.s, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f32_x, svfloat32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c
index b397da8..6501b86 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c
@@ -13,7 +13,7 @@ TEST_UNIFORM_Z (dup_1_f64, svfloat64_t,
 
 /*
 ** dup_0_f64:
-**	mov	z0\.d, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f64, svfloat64_t,
@@ -118,7 +118,7 @@ TEST_UNIFORM_Z (dup_1_f64_z, svfloat64_t,
 
 /*
 ** dup_0_f64_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f64_z, svfloat64_t,
@@ -166,7 +166,7 @@ TEST_UNIFORM_Z (dup_1_f64_x, svfloat64_t,
 
 /*
 ** dup_0_f64_x:
-**	mov	z0\.d, #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_f64_x, svfloat64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c
index 9c91a5b..5bcd3b4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c
@@ -612,13 +612,13 @@ TEST_UNIFORM_Z (dup_127_s16_z, svint16_t,
 /*
 ** dup_128_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #128
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #128
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -639,13 +639,13 @@ TEST_UNIFORM_Z (dup_253_s16_z, svint16_t,
 /*
 ** dup_254_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #254
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #254
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -656,13 +656,13 @@ TEST_UNIFORM_Z (dup_254_s16_z, svint16_t,
 /*
 ** dup_255_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #255
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -682,13 +682,13 @@ TEST_UNIFORM_Z (dup_256_s16_z, svint16_t,
 /*
 ** dup_257_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+)\.b, #1
-**	sel	z0\.h, p0, \2\.h, \1\.h
+**	sel	z0\.h, p0, \2\.h, z\1\.h
 ** |
 **	mov	(z[0-9]+)\.b, #1
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3\.h, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3\.h, z\4\.h
 ** )
 **	ret
 */
@@ -727,13 +727,13 @@ TEST_UNIFORM_Z (dup_7ffd_s16_z, svint16_t,
 /*
 ** dup_7ffe_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #32766
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #32766
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -744,13 +744,13 @@ TEST_UNIFORM_Z (dup_7ffe_s16_z, svint16_t,
 /*
 ** dup_7fff_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #32767
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -779,13 +779,13 @@ TEST_UNIFORM_Z (dup_m128_s16_z, svint16_t,
 /*
 ** dup_m129_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-129
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-129
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -806,13 +806,13 @@ TEST_UNIFORM_Z (dup_m254_s16_z, svint16_t,
 /*
 ** dup_m255_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-255
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -832,13 +832,13 @@ TEST_UNIFORM_Z (dup_m256_s16_z, svint16_t,
 /*
 ** dup_m257_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-257
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-257
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -849,13 +849,13 @@ TEST_UNIFORM_Z (dup_m257_s16_z, svint16_t,
 /*
 ** dup_m258_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+)\.b, #-2
-**	sel	z0\.h, p0, \2\.h, \1\.h
+**	sel	z0\.h, p0, \2\.h, z\1\.h
 ** |
 **	mov	(z[0-9]+)\.b, #-2
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3\.h, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3\.h, z\4\.h
 ** )
 **	ret
 */
@@ -889,13 +889,13 @@ TEST_UNIFORM_Z (dup_m7f00_s16_z, svint16_t,
 /*
 ** dup_m7f01_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-32513
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-32513
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -916,13 +916,13 @@ TEST_UNIFORM_Z (dup_m7ffe_s16_z, svint16_t,
 /*
 ** dup_m7fff_s16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-32767
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -941,7 +941,7 @@ TEST_UNIFORM_Z (dup_m8000_s16_z, svint16_t,
 
 /*
 ** dup_0_s16_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_s16_z, svint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c
index 1cfecd9..b9cb1e5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c
@@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_s32_z, svint32_t,
 /*
 ** dup_128_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #128
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #128
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_s32_z, svint32_t,
 /*
 ** dup_254_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #254
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #254
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_s32_z, svint32_t,
 /*
 ** dup_255_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #255
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_s32_z, svint32_t,
 /*
 ** dup_7ffe_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #32766
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #32766
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_s32_z, svint32_t,
 /*
 ** dup_7fff_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #32767
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_s32_z, svint32_t,
 /*
 ** dup_m129_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-129
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-129
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_s32_z, svint32_t,
 /*
 ** dup_m255_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-255
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_s32_z, svint32_t,
 /*
 ** dup_m257_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-257
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-257
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_s32_z, svint32_t,
 /*
 ** dup_m7f01_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-32513
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-32513
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_s32_z, svint32_t,
 /*
 ** dup_m7fff_s32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-32767
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_s32_z, svint32_t,
 
 /*
 ** dup_0_s32_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_s32_z, svint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c
index 5189dcf..0227184 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c
@@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_s64_z, svint64_t,
 /*
 ** dup_128_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #128
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #128
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_s64_z, svint64_t,
 /*
 ** dup_254_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #254
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #254
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_s64_z, svint64_t,
 /*
 ** dup_255_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #255
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_s64_z, svint64_t,
 /*
 ** dup_7ffe_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #32766
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #32766
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_s64_z, svint64_t,
 /*
 ** dup_7fff_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #32767
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_s64_z, svint64_t,
 /*
 ** dup_m129_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-129
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-129
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_s64_z, svint64_t,
 /*
 ** dup_m255_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-255
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_s64_z, svint64_t,
 /*
 ** dup_m257_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-257
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-257
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_s64_z, svint64_t,
 /*
 ** dup_m7f01_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-32513
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-32513
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_s64_z, svint64_t,
 /*
 ** dup_m7fff_s64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-32767
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_s64_z, svint64_t,
 
 /*
 ** dup_0_s64_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_s64_z, svint64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c
index f3c9db8..66c8c92 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c
@@ -275,7 +275,7 @@ TEST_UNIFORM_Z (dup_m128_s8_z, svint8_t,
 
 /*
 ** dup_0_s8_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_s8_z, svint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c
index 09fecd4..284d047 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c
@@ -612,13 +612,13 @@ TEST_UNIFORM_Z (dup_127_u16_z, svuint16_t,
 /*
 ** dup_128_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #128
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #128
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -639,13 +639,13 @@ TEST_UNIFORM_Z (dup_253_u16_z, svuint16_t,
 /*
 ** dup_254_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #254
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #254
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -656,13 +656,13 @@ TEST_UNIFORM_Z (dup_254_u16_z, svuint16_t,
 /*
 ** dup_255_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #255
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -682,13 +682,13 @@ TEST_UNIFORM_Z (dup_256_u16_z, svuint16_t,
 /*
 ** dup_257_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+)\.b, #1
-**	sel	z0\.h, p0, \2\.h, \1\.h
+**	sel	z0\.h, p0, \2\.h, z\1\.h
 ** |
 **	mov	(z[0-9]+)\.b, #1
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3\.h, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3\.h, z\4\.h
 ** )
 **	ret
 */
@@ -727,13 +727,13 @@ TEST_UNIFORM_Z (dup_7ffd_u16_z, svuint16_t,
 /*
 ** dup_7ffe_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #32766
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #32766
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -744,13 +744,13 @@ TEST_UNIFORM_Z (dup_7ffe_u16_z, svuint16_t,
 /*
 ** dup_7fff_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #32767
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -779,13 +779,13 @@ TEST_UNIFORM_Z (dup_m128_u16_z, svuint16_t,
 /*
 ** dup_m129_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-129
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-129
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -806,13 +806,13 @@ TEST_UNIFORM_Z (dup_m254_u16_z, svuint16_t,
 /*
 ** dup_m255_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-255
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -832,13 +832,13 @@ TEST_UNIFORM_Z (dup_m256_u16_z, svuint16_t,
 /*
 ** dup_m257_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-257
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-257
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -849,13 +849,13 @@ TEST_UNIFORM_Z (dup_m257_u16_z, svuint16_t,
 /*
 ** dup_m258_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+)\.b, #-2
-**	sel	z0\.h, p0, \2\.h, \1\.h
+**	sel	z0\.h, p0, \2\.h, z\1\.h
 ** |
 **	mov	(z[0-9]+)\.b, #-2
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3\.h, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3\.h, z\4\.h
 ** )
 **	ret
 */
@@ -889,13 +889,13 @@ TEST_UNIFORM_Z (dup_m7f00_u16_z, svuint16_t,
 /*
 ** dup_m7f01_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-32513
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-32513
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -916,13 +916,13 @@ TEST_UNIFORM_Z (dup_m7ffe_u16_z, svuint16_t,
 /*
 ** dup_m7fff_u16_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.h), #-32767
-**	sel	z0\.h, p0, \2, \1\.h
+**	sel	z0\.h, p0, \2, z\1\.h
 ** |
 **	mov	(z[0-9]+\.h), #-32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.h, p0, \3, \4\.h
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.h, p0, \3, z\4\.h
 ** )
 **	ret
 */
@@ -941,7 +941,7 @@ TEST_UNIFORM_Z (dup_m8000_u16_z, svuint16_t,
 
 /*
 ** dup_0_u16_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_u16_z, svuint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c
index 4b7da13..77f39cc 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c
@@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_u32_z, svuint32_t,
 /*
 ** dup_128_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #128
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #128
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_u32_z, svuint32_t,
 /*
 ** dup_254_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #254
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #254
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_u32_z, svuint32_t,
 /*
 ** dup_255_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #255
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_u32_z, svuint32_t,
 /*
 ** dup_7ffe_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #32766
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #32766
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_u32_z, svuint32_t,
 /*
 ** dup_7fff_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #32767
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_u32_z, svuint32_t,
 /*
 ** dup_m129_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-129
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-129
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_u32_z, svuint32_t,
 /*
 ** dup_m255_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-255
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_u32_z, svuint32_t,
 /*
 ** dup_m257_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-257
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-257
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_u32_z, svuint32_t,
 /*
 ** dup_m7f01_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-32513
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-32513
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_u32_z, svuint32_t,
 /*
 ** dup_m7fff_u32_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.s), #-32767
-**	sel	z0\.s, p0, \2, \1\.s
+**	sel	z0\.s, p0, \2, z\1\.s
 ** |
 **	mov	(z[0-9]+\.s), #-32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.s, p0, \3, \4\.s
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.s, p0, \3, z\4\.s
 ** )
 **	ret
 */
@@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_u32_z, svuint32_t,
 
 /*
 ** dup_0_u32_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_u32_z, svuint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c
index 4d64b40..8b5f458 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c
@@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_u64_z, svuint64_t,
 /*
 ** dup_128_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #128
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #128
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_u64_z, svuint64_t,
 /*
 ** dup_254_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #254
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #254
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_u64_z, svuint64_t,
 /*
 ** dup_255_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #255
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_u64_z, svuint64_t,
 /*
 ** dup_7ffe_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #32766
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #32766
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_u64_z, svuint64_t,
 /*
 ** dup_7fff_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #32767
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_u64_z, svuint64_t,
 /*
 ** dup_m129_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-129
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-129
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_u64_z, svuint64_t,
 /*
 ** dup_m255_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-255
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-255
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_u64_z, svuint64_t,
 /*
 ** dup_m257_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-257
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-257
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_u64_z, svuint64_t,
 /*
 ** dup_m7f01_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-32513
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-32513
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_u64_z, svuint64_t,
 /*
 ** dup_m7fff_u64_z:
 ** (
-**	mov	(z[0-9]+)\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	mov	(z[0-9]+\.d), #-32767
-**	sel	z0\.d, p0, \2, \1\.d
+**	sel	z0\.d, p0, \2, z\1\.d
 ** |
 **	mov	(z[0-9]+\.d), #-32767
-**	mov	(z[0-9]+)\.b, #0
-**	sel	z0\.d, p0, \3, \4\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sel	z0\.d, p0, \3, z\4\.d
 ** )
 **	ret
 */
@@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_u64_z, svuint64_t,
 
 /*
 ** dup_0_u64_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_u64_z, svuint64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c
index 1bb4cc1..8f2be55 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c
@@ -275,7 +275,7 @@ TEST_UNIFORM_Z (dup_m128_u8_z, svuint8_t,
 
 /*
 ** dup_0_u8_z:
-**	mov	z0\.[bhsd], #0
+**	movi?	[vdz]0\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 TEST_UNIFORM_Z (dup_0_u8_z, svuint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c
index 92e0005..0667f47 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c
@@ -15,7 +15,7 @@ svint64_t s64_x_pg (svbool_t pg)
 
 /*
 ** s64_x_pg_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_0 (svbool_t pg)
@@ -25,7 +25,7 @@ svint64_t s64_x_pg_0 (svbool_t pg)
 
 /*
 ** s64_x_pg_by0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_by0 (svbool_t pg)
@@ -45,7 +45,7 @@ svint64_t s64_z_pg (svbool_t pg)
 
 /*
 ** s64_z_pg_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_0 (svbool_t pg)
@@ -55,7 +55,7 @@ svint64_t s64_z_pg_0 (svbool_t pg)
 
 /*
 ** s64_z_pg_by0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_by0 (svbool_t pg)
@@ -117,7 +117,7 @@ svint64_t s64_x_pg_n (svbool_t pg)
 
 /*
 ** s64_x_pg_n_s64_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_n_s64_0 (svbool_t pg)
@@ -127,7 +127,7 @@ svint64_t s64_x_pg_n_s64_0 (svbool_t pg)
 
 /*
 ** s64_x_pg_n_s64_by0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_n_s64_by0 (svbool_t pg)
@@ -147,7 +147,7 @@ svint64_t s64_z_pg_n (svbool_t pg)
 
 /*
 ** s64_z_pg_n_s64_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_n_s64_0 (svbool_t pg)
@@ -157,7 +157,7 @@ svint64_t s64_z_pg_n_s64_0 (svbool_t pg)
 
 /*
 ** s64_z_pg_n_s64_by0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_n_s64_by0 (svbool_t pg)
@@ -209,7 +209,7 @@ svint64_t s64_m_ptrue_n ()
 
 /*
 ** s32_m_ptrue_dupq:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint32_t s32_m_ptrue_dupq ()
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c
index 2a00cab..07f161a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c
@@ -15,7 +15,7 @@ svint64_t s64_x_pg (svbool_t pg)
 
 /*
 ** s64_x_pg_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_0 (svbool_t pg)
@@ -35,7 +35,7 @@ svint64_t s64_z_pg (svbool_t pg)
 
 /*
 ** s64_z_pg_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_0 (svbool_t pg)
@@ -97,7 +97,7 @@ svint64_t s64_x_pg_n (svbool_t pg)
 
 /*
 ** s64_x_pg_n_s64_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_n_s64_0 (svbool_t pg)
@@ -117,7 +117,7 @@ svint64_t s64_z_pg_n (svbool_t pg)
 
 /*
 ** s64_z_pg_n_s64_0:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_n_s64_0 (svbool_t pg)
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c
index 3b8854e..663e988 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c
@@ -99,7 +99,7 @@ DEF_SET_IMM (int32_t, -32763, imm_m32763)
 
 /* { dg-final { scan-assembler {\tmov\tz[0-9]+\.b, #-1\n} } } */
 
-/* { dg-final { scan-assembler {\tmov\tz[0-9]+\.b, #0\n} } } */
+/* { dg-final { scan-assembler {\tmov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0\n} } } */
 
 /* { dg-final { scan-assembler {\tmov\tz[0-9]+\.b, #1\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz[0-9]+\.h, #1\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c
index c13efd8..51a5e39 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c
@@ -47,8 +47,6 @@ DEF_SET_IMM_FP (0x1.1fp-4, imm1fpm4)
 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #3.1e\+1\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2.421875e-1\n} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, #0\n} 1 } } */
-
 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d,} 7 } } */
 
 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #1.0e\+0\n} 1 } } */
@@ -59,4 +57,4 @@ DEF_SET_IMM_FP (0x1.1fp-4, imm1fpm4)
 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3.1e\+1\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2.421875e-1\n} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #0\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tmov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c b/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c
index 0dcd018..f1235fc 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c
@@ -5,7 +5,7 @@
 
 /*
 ** s64_x_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2)
@@ -15,7 +15,7 @@ svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2)
 
 /*
 ** s64_z_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2)
@@ -25,7 +25,7 @@ svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2)
 
 /*
 ** s64_m_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2)
@@ -35,7 +35,7 @@ svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2)
 
 /*
 ** s64_x_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_ptrue_op1 (svint64_t op2)
@@ -45,7 +45,7 @@ svint64_t s64_x_ptrue_op1 (svint64_t op2)
 
 /*
 ** s64_z_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_ptrue_op1 (svint64_t op2)
@@ -55,7 +55,7 @@ svint64_t s64_z_ptrue_op1 (svint64_t op2)
 
 /*
 ** s64_m_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_m_ptrue_op1 (svint64_t op2)
@@ -65,7 +65,7 @@ svint64_t s64_m_ptrue_op1 (svint64_t op2)
 
 /*
 ** s64_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1)
@@ -75,7 +75,7 @@ svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_op2 (svbool_t pg, svint64_t op1)
@@ -85,8 +85,8 @@ svint64_t s64_z_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_m_pg_op2:
-**	mov	(z[0-9]+)\.b, #0
-**	sdiv	(z[0-9]\.d), p[0-7]/m, \2, \1\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sdiv	(z[0-9]\.d), p[0-7]/m, \2, z\1\.d
 **	ret
 */
 svint64_t s64_m_pg_op2 (svbool_t pg, svint64_t op1)
@@ -96,7 +96,7 @@ svint64_t s64_m_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_ptrue_op2 (svint64_t op1)
@@ -106,7 +106,7 @@ svint64_t s64_x_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_ptrue_op2 (svint64_t op1)
@@ -116,7 +116,7 @@ svint64_t s64_z_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_m_ptrue_op2 (svint64_t op1)
@@ -126,7 +126,7 @@ svint64_t s64_m_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_n_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1)
@@ -136,7 +136,7 @@ svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_n_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_z_pg_op2 (svbool_t pg, svint64_t op1)
@@ -146,8 +146,8 @@ svint64_t s64_n_z_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_n_m_pg_op2:
-**	mov	(z[0-9]+)\.b, #0
-**	sdiv	(z[0-9]+\.d), p[0-7]/m, \2, \1\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	sdiv	(z[0-9]+\.d), p[0-7]/m, \2, z\1\.d
 **	ret
 */
 svint64_t s64_n_m_pg_op2 (svbool_t pg, svint64_t op1)
@@ -157,7 +157,7 @@ svint64_t s64_n_m_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_n_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_x_ptrue_op2 (svint64_t op1)
@@ -167,7 +167,7 @@ svint64_t s64_n_x_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_n_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_z_ptrue_op2 (svint64_t op1)
@@ -177,7 +177,7 @@ svint64_t s64_n_z_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_n_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_m_ptrue_op2 (svint64_t op1)
@@ -187,7 +187,7 @@ svint64_t s64_n_m_ptrue_op2 (svint64_t op1)
 
 /*
 ** u64_x_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2)
@@ -197,7 +197,7 @@ svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2)
 
 /*
 ** u64_z_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2)
@@ -207,7 +207,7 @@ svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2)
 
 /*
 ** u64_m_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2)
@@ -217,7 +217,7 @@ svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2)
 
 /*
 ** u64_x_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_ptrue_op1 (svuint64_t op2)
@@ -227,7 +227,7 @@ svuint64_t u64_x_ptrue_op1 (svuint64_t op2)
 
 /*
 ** u64_z_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_ptrue_op1 (svuint64_t op2)
@@ -237,7 +237,7 @@ svuint64_t u64_z_ptrue_op1 (svuint64_t op2)
 
 /*
 ** u64_m_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_m_ptrue_op1 (svuint64_t op2)
@@ -247,7 +247,7 @@ svuint64_t u64_m_ptrue_op1 (svuint64_t op2)
 
 /*
 ** u64_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -257,7 +257,7 @@ svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -267,8 +267,8 @@ svuint64_t u64_z_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_m_pg_op2:
-**	mov	(z[0-9]+)\.b, #0
-**	udiv	(z[0-9]+\.d), p[0-7]/m, \2, \1\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	udiv	(z[0-9]+\.d), p[0-7]/m, \2, z\1\.d
 **	ret
 */
 svuint64_t u64_m_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -278,7 +278,7 @@ svuint64_t u64_m_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_ptrue_op2 (svuint64_t op1)
@@ -288,7 +288,7 @@ svuint64_t u64_x_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_ptrue_op2 (svuint64_t op1)
@@ -298,7 +298,7 @@ svuint64_t u64_z_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_m_ptrue_op2 (svuint64_t op1)
@@ -308,7 +308,7 @@ svuint64_t u64_m_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_n_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -318,7 +318,7 @@ svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_n_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_z_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -328,8 +328,8 @@ svuint64_t u64_n_z_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_n_m_pg_op2:
-**	mov	(z[0-9]+)\.b, #0
-**	udiv	(z[0-9]+\.d), p[0-7]/m, \2, \1\.d
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
+**	udiv	(z[0-9]+\.d), p[0-7]/m, \2, z\1\.d
 **	ret
 */
 svuint64_t u64_n_m_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -339,7 +339,7 @@ svuint64_t u64_n_m_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_n_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1)
@@ -349,7 +349,7 @@ svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_n_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1)
@@ -359,7 +359,7 @@ svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_n_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_m_ptrue_op2 (svuint64_t op1)
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c b/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c
index a5674fd..5aa2376 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c
@@ -5,7 +5,7 @@
 
 /*
 ** s64_x_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2)
@@ -15,7 +15,7 @@ svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2)
 
 /*
 ** s64_z_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2)
@@ -25,7 +25,7 @@ svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2)
 
 /*
 ** s64_m_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2)
@@ -35,7 +35,7 @@ svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2)
 
 /*
 ** s64_x_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_ptrue_op1 (svint64_t op2)
@@ -45,7 +45,7 @@ svint64_t s64_x_ptrue_op1 (svint64_t op2)
 
 /*
 ** s64_z_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_ptrue_op1 (svint64_t op2)
@@ -55,7 +55,7 @@ svint64_t s64_z_ptrue_op1 (svint64_t op2)
 
 /*
 ** s64_m_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_m_ptrue_op1 (svint64_t op2)
@@ -65,7 +65,7 @@ svint64_t s64_m_ptrue_op1 (svint64_t op2)
 
 /*
 ** s64_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1)
@@ -75,7 +75,7 @@ svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_pg_op2 (svbool_t pg, svint64_t op1)
@@ -95,7 +95,7 @@ svint64_t s64_m_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_x_ptrue_op2 (svint64_t op1)
@@ -105,7 +105,7 @@ svint64_t s64_x_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_z_ptrue_op2 (svint64_t op1)
@@ -115,7 +115,7 @@ svint64_t s64_z_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_m_ptrue_op2 (svint64_t op1)
@@ -125,7 +125,7 @@ svint64_t s64_m_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_n_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1)
@@ -135,7 +135,7 @@ svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_n_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_z_pg_op2 (svbool_t pg, svint64_t op1)
@@ -155,7 +155,7 @@ svint64_t s64_n_m_pg_op2 (svbool_t pg, svint64_t op1)
 
 /*
 ** s64_n_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_x_ptrue_op2 (svint64_t op1)
@@ -165,7 +165,7 @@ svint64_t s64_n_x_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_n_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_z_ptrue_op2 (svint64_t op1)
@@ -175,7 +175,7 @@ svint64_t s64_n_z_ptrue_op2 (svint64_t op1)
 
 /*
 ** s64_n_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svint64_t s64_n_m_ptrue_op2 (svint64_t op1)
@@ -185,7 +185,7 @@ svint64_t s64_n_m_ptrue_op2 (svint64_t op1)
 
 /*
 ** u64_x_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2)
@@ -195,7 +195,7 @@ svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2)
 
 /*
 ** u64_z_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2)
@@ -205,7 +205,7 @@ svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2)
 
 /*
 ** u64_m_pg_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2)
@@ -215,7 +215,7 @@ svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2)
 
 /*
 ** u64_x_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_ptrue_op1 (svuint64_t op2)
@@ -225,7 +225,7 @@ svuint64_t u64_x_ptrue_op1 (svuint64_t op2)
 
 /*
 ** u64_z_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_ptrue_op1 (svuint64_t op2)
@@ -235,7 +235,7 @@ svuint64_t u64_z_ptrue_op1 (svuint64_t op2)
 
 /*
 ** u64_m_ptrue_op1:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_m_ptrue_op1 (svuint64_t op2)
@@ -245,7 +245,7 @@ svuint64_t u64_m_ptrue_op1 (svuint64_t op2)
 
 /*
 ** u64_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -255,7 +255,7 @@ svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -275,7 +275,7 @@ svuint64_t u64_m_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_x_ptrue_op2 (svuint64_t op1)
@@ -285,7 +285,7 @@ svuint64_t u64_x_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_z_ptrue_op2 (svuint64_t op1)
@@ -295,7 +295,7 @@ svuint64_t u64_z_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_m_ptrue_op2 (svuint64_t op1)
@@ -305,7 +305,7 @@ svuint64_t u64_m_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_n_x_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -315,7 +315,7 @@ svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_n_z_pg_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_z_pg_op2 (svbool_t pg, svuint64_t op1)
@@ -335,7 +335,7 @@ svuint64_t u64_n_m_pg_op2 (svbool_t pg, svuint64_t op1)
 
 /*
 ** u64_n_x_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1)
@@ -345,7 +345,7 @@ svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_n_z_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1)
@@ -355,7 +355,7 @@ svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1)
 
 /*
 ** u64_n_m_ptrue_op2:
-**	mov	z[0-9]+\.b, #0
+**	movi?	[vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0
 **	ret
 */
 svuint64_t u64_n_m_ptrue_op2 (svuint64_t op1)
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c
index 3ad4454..6cc1be0 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c
@@ -55,7 +55,7 @@ caller_int (int8_t *x0, int16_t *x1, int32_t *x2, int64_t *x3)
 	      svptrue_pat_b32 (SV_VL3));
 }
 
-/* { dg-final { scan-assembler {\tmov\tz0\.b, #0\n} } } */
+/* { dg-final { scan-assembler {\tmov(\tz0\.b|i\td0), #0\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz1\.h, #1\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz2\.s, #2\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz3\.d, #3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c
index 56896c9..86d8204 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c
@@ -55,7 +55,7 @@ caller_uint (uint8_t *x0, uint16_t *x1, uint32_t *x2, uint64_t *x3)
 	       svptrue_pat_b32 (SV_VL3));
 }
 
-/* { dg-final { scan-assembler {\tmov\tz0\.b, #0\n} } } */
+/* { dg-final { scan-assembler {\tmov(\tz0\.b|i\td0), #0\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz1\.h, #1\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz2\.s, #2\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz3\.d, #3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c
index 7213c86..5b6120d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c
@@ -55,7 +55,7 @@ caller_float (float16_t *x0, float16_t *x1, float32_t *x2, float64_t *x3)
 		svptrue_pat_b32 (SV_VL3));
 }
 
-/* { dg-final { scan-assembler {\tmov\tz0\.[bhsd], #0\n} } } */
+/* { dg-final { scan-assembler {\tmov(\tz0\.[bhsd]|i\td0), #0\n} } } */
 /* { dg-final { scan-assembler {\tfmov\tz1\.h, #1\.0} } } */
 /* { dg-final { scan-assembler {\tfmov\tz2\.s, #2\.0} } } */
 /* { dg-final { scan-assembler {\tfmov\tz3\.d, #3\.0} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c b/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
index a51aa33..f9f7ecf 100644
--- a/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
@@ -14,5 +14,5 @@ foo (double *output)
     output[i] = 0.0;
 }
 
-/* { dg-final { scan-assembler "movi\\tv\[0-9\]+\\.2d, 0" } } */
+/* { dg-final { scan-assembler {movi\tv[0-9]+\.\d+[bhsd], 0} } } */
 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */