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| author | Tamar Christina <tamar.christina@arm.com> | 2025-04-16 13:11:20 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2025-04-16 13:11:20 +0100 |
| commit | fa99720e9f3447565d274baaa81e23c2ddab4a67 (patch) | |
| tree | 452dd6d958d6986ce4dcdf8c9bea12b6a7eec901 | |
| parent | 46ccce1de686c1b437eff43431dc20d20d4687c0 (diff) | |
| download | gcc-fa99720e9f3447565d274baaa81e23c2ddab4a67.zip gcc-fa99720e9f3447565d274baaa81e23c2ddab4a67.tar.gz gcc-fa99720e9f3447565d274baaa81e23c2ddab4a67.tar.bz2 | |
middle-end: force AMDGCN test for vect-early-break_18.c to consistent architecture [PR119286]
The given test is intended to test vectorization of a strided access done by
having a step of > 1.
GCN target doesn't support load lanes, so the testcase is expected to fail,
other targets create a permuted load here which we then then reject.
However some GCN arch don't seem to support the permuted loads either, so the
vectorizer tries a gather/scatter. But the indices aren't supported by some
target, so instead the vectorizer scalarizes the loads.
I can't really test for which architecture is being used by the compiler, so
instead this updates the testcase to use one single architecture so we get a
consistent result.
gcc/testsuite/ChangeLog:
PR target/119286
* gcc.dg/vect/vect-early-break_18.c: Force -march=gfx908 for amdgcn.
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-early-break_18.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_18.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_18.c index edddb44..cd39704 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_18.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_18.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target vect_early_break } */ /* { dg-require-effective-target vect_int } */ - +/* { dg-additional-options "-march=gfx908" { target amdgcn*-*-* } } */ /* { dg-additional-options "-Ofast" } */ /* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target vect_load_lanes } } } */ |