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| author | Robin Dapp <rdapp.gcc@gmail.com> | 2025-02-15 08:48:06 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-02-15 08:48:06 -0700 |
| commit | f9868e623fc80c6c6260c9dc6c7280db90433207 (patch) | |
| tree | dd667fde0adee61c53cfda13694129539c26d7ff | |
| parent | ad3de70fd863e32ea6440bcb613ffe2c58c2dae8 (diff) | |
| download | gcc-f9868e623fc80c6c6260c9dc6c7280db90433207.zip gcc-f9868e623fc80c6c6260c9dc6c7280db90433207.tar.gz gcc-f9868e623fc80c6c6260c9dc6c7280db90433207.tar.bz2 | |
[PATCH] RISC-V: testsuite: Adjust pr117722.c scan.
the test scanned for vmin and vmax instead of vminu and vmaxu.
This patch fixes that.
Will commit as obvious once the CI is OK with it.
Regards
Robin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr117722.c: Scan for vminu and
vmaxu.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c index b675930..f255ceb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c @@ -18,6 +18,6 @@ int pixel_sad_n(unsigned char *pix1, unsigned char *pix2, int n) return sum; } -/* { dg-final { scan-assembler {vmin\.v} } } */ -/* { dg-final { scan-assembler {vmax\.v} } } */ +/* { dg-final { scan-assembler {vminu\.v} } } */ +/* { dg-final { scan-assembler {vmaxu\.v} } } */ /* { dg-final { scan-assembler {vsub\.v} } } */ |