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| author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-10-02 08:11:07 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-10-02 08:11:07 +0000 |
| commit | f25a140b6a8a27a1bfb2d2572b4963d098ff91ae (patch) | |
| tree | 82837fb50e3f7cc47707097144b55a86e3241788 | |
| parent | 0389d86c4e252df643f9c3539e5a114add56ec7f (diff) | |
| download | gcc-f25a140b6a8a27a1bfb2d2572b4963d098ff91ae.zip gcc-f25a140b6a8a27a1bfb2d2572b4963d098ff91ae.tar.gz gcc-f25a140b6a8a27a1bfb2d2572b4963d098ff91ae.tar.bz2 | |
[AArch64] PR71307: Define union class of POINTER+FP
ALL_REGS doesn't function as a union class of POINTER_REGS and FP_REGS
since it includes the CC register as well. REGNO_REG_CLASS (CC_REGNUM)
is NO_REGS, but of course NO_REGS rightly doesn't include CC_REGNUM.
Adding a union class for POINTER+FP allows the RA to use it as the
preferred or alternative class of a pseudo. It also works as a
union class of GENERAL+FP for modes that aren't allowed in SP.
This is also needed for the SVE port, which adds predicate registers
to the mix.
2017-09-15 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
PR target/71307
* config/aarch64/aarch64.h (POINTER_AND_FP_REGS): New reg class.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
POINTER_AND_FP_REGS.
gcc/testsuite/
PR target/71307
* gcc.target/aarch64/vect_copy_lane_1.c: Remove XFAIL.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r253337
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 1 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.h | 3 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c | 3 |
5 files changed, 22 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d5b0b6f..4515802 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-10-02 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + + PR target/71307 + * config/aarch64/aarch64.h (POINTER_AND_FP_REGS): New reg class. + (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly. + * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle + POINTER_AND_FP_REGS. + 2017-10-02 Richard Biener <rguenther@suse.de> PR tree-optimization/82355 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 23f5aff..e89c815 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -6022,6 +6022,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode) case POINTER_REGS: case GENERAL_REGS: case ALL_REGS: + case POINTER_AND_FP_REGS: case FP_REGS: case FP_LO_REGS: return diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 0786b28..1c3aff5 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -444,6 +444,7 @@ enum reg_class POINTER_REGS, FP_LO_REGS, FP_REGS, + POINTER_AND_FP_REGS, ALL_REGS, LIM_REG_CLASSES /* Last */ }; @@ -459,6 +460,7 @@ enum reg_class "POINTER_REGS", \ "FP_LO_REGS", \ "FP_REGS", \ + "POINTER_AND_FP_REGS", \ "ALL_REGS" \ } @@ -471,6 +473,7 @@ enum reg_class { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ + { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2faad379..992ac3c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-10-02 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + + PR target/71307 + * gcc.target/aarch64/vect_copy_lane_1.c: Remove XFAIL. + 2017-10-02 Richard Biener <rguenther@suse.de> PR tree-optimization/82355 diff --git a/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c b/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c index e144def..2848be5 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c @@ -45,8 +45,7 @@ BUILD_TEST (uint32x2_t, uint32x4_t, , q, u32, 1, 3) BUILD_TEST (float64x1_t, float64x2_t, , q, f64, 0, 1) BUILD_TEST (int64x1_t, int64x2_t, , q, s64, 0, 1) BUILD_TEST (uint64x1_t, uint64x2_t, , q, u64, 0, 1) -/* XFAIL due to PR 71307. */ -/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 } } */ /* vcopyq_lane. */ BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7) |