RISC-V: Support -mcpu for XiangShan Kunminghu cpu.

This patch adds support for the XiangShan Kunminghu CPU in GCC, allowing
the use of the `-mcpu=xiangshan-kunminghu` option.

XiangShan-KunMingHu is the third-generation open-source high-performance
RISC-V processor.[1] You can find the corresponding ISA extension from the
XiangShan Github repository.[2] The latest news of KunMingHu can be found
in the XiangShan Biweekly.[3]

[1] https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
[2] https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala
[3] https://docs.xiangshan.cc/zh-cn/latest/blog

A dedicated scheduling model for KunMingHu's hybrid pipeline will be
proposed in a subsequent PR.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): New cpu tune.
	(RISCV_CORE): New cpu.
	* doc/invoke.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-xiangshan-kunminghu.c: New test.

Co-Authored-By: Jiawei Chen <jiawei@iscas.ac.cn>
Co-Authored-By: Yangyu Chen <cyy@cyyself.name>
Co-Authored-By: Tang Haojin <tanghaojin@outlook.com>

3 files changed, 111 insertions, 2 deletions

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 118fef2..cff7c77 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -48,6 +48,7 @@ RISCV_TUNE("xt-c910v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xt-c920", generic, generic_ooo_tune_info)
 RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
+RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
 RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)
@@ -154,6 +155,19 @@ RISCV_CORE("xiangshan-nanhu",      "rv64imafdc_zba_zbb_zbc_zbs_"
 			      "svinval_zicbom_zicboz",
 			      "xiangshan-nanhu")
 
+RISCV_CORE("xiangshan-kunminghu",   "rv64imafdcbvh_sdtrig_sha_shcounterenw_"
+			      "shgatpa_shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd_"
+			      "smaia_smcsrind_smdbltrp_smmpm_smnpm_smrnmi_smstateen_"
+			      "ssaia_ssccptr_sscofpmf_sscounterenw_sscsrind_ssdbltrp_"
+			      "ssnpm_sspm_ssstateen_ssstrict_sstc_sstvala_sstvecd_"
+			      "ssu64xl_supm_svade_svbare_svinval_svnapot_svpbmt_za64rs_"
+			      "zacas_zawrs_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zcb_zcmop_"
+			      "zfa_zfh_zfhmin_zic64b_zicbom_zicbop_zicboz_ziccif_"
+			      "zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintpause_"
+			      "zihpm_zimop_zkn_zknd_zkne_zknh_zksed_zksh_zkt_zvbb_zvfh_"
+			      "zvfhmin_zvkt_zvl128b_zvl32b_zvl64b",
+			      "xiangshan-kunminghu")
+
 RISCV_CORE("mips-p8700",     	"rv64imafd_zicsr_zmmul_"
 			      "zaamo_zalrsc_zba_zbb",
 			      "mips-p8700")
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f943d3a..d7f51b4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31200,8 +31200,8 @@ Permissible values for this option are: @samp{mips-p8700}, @samp{sifive-e20},
 @samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54},
 @samp{sifive-s76}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280},
 @samp{sifive-xp450}, @samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8},
-@samp{xiangshan-nanhu}, @samp{xt-c908}, @samp{xt-c908v}, @samp{xt-c910}, @samp{xt-c910v2},
-@samp{xt-c920}, @samp{xt-c920v2}.
+@samp{xiangshan-nanhu}, @samp{xiangshan-kunminghu}, @samp{xt-c908}, @samp{xt-c908v},
+@samp{xt-c910}, @samp{xt-c910v2}, @samp{xt-c920}, @samp{xt-c920v2}.
 
 Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}.
 
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c
new file mode 100644
index 0000000..e3ae65c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c
@@ -0,0 +1,95 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xiangshan-kunminghu" } */
+/* XiangShan Kunminghu => rv64imafdcbvh_sdtrig_sha_shcounterenw_shgatpa
+                      _shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd
+                      _smaia_smcsrind_smdbltrp_smmpm_smnpm_smrnmi_smstateen
+                      _ssaia_ssccptr_sscofpmf_sscounterenw_sscsrind_ssdbltrp
+                      _ssnpm_sspm_ssstateen_ssstrict_sstc_sstvala_sstvecd
+                      _ssu64xl_supm_svade_svbare_svinval_svnapot_svpbmt
+                      _za64rs_zacas_zawrs_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zcb
+                      _zcmop_zfa_zfh_zfhmin_zic64b_zicbom_zicbop_zicboz_ziccif
+                      _zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintpause
+                      _zihpm_zimop_zkn_zknd_zkne_zknh_zksed_zksh_zkt_zvbb
+                      _zvfh_zvfhmin_zvkt_zvl128b_zvl32b_zvl64b */
+
+#if !((__riscv_xlen == 64)		\
+      && !defined(__riscv_32e)		\
+      && defined(__riscv_mul)		\
+      && defined(__riscv_atomic)	\
+      && (__riscv_flen == 64)		\
+      && defined(__riscv_compressed)	\
+      && defined(__riscv_v)		\
+      && defined(__riscv_zic64b)	\
+      && defined(__riscv_zicbom)	\
+      && defined(__riscv_zicbop)	\
+      && defined(__riscv_zicboz)	\
+      && defined(__riscv_ziccif)	\
+      && defined(__riscv_zicclsm)	\
+      && defined(__riscv_ziccrse)	\
+      && defined(__riscv_zicntr)	\
+      && defined(__riscv_zicond)	\
+      && defined(__riscv_zicsr)	\
+      && defined(__riscv_zifencei)	\
+      && defined(__riscv_zihintpause)	\
+      && defined(__riscv_zihpm)	\
+      && defined(__riscv_zimop)	\
+      && defined(__riscv_za64rs)	\
+      && defined(__riscv_zacas)	\
+      && defined(__riscv_zawrs)	\
+      && defined(__riscv_zba)	\
+      && defined(__riscv_zbb)	\
+      && defined(__riscv_zbc)	\
+      && defined(__riscv_zbs)	\
+      && defined(__riscv_zbkb)	\
+      && defined(__riscv_zbkc)	\
+      && defined(__riscv_zbkx)	\
+      && defined(__riscv_zcb)	\
+      && defined(__riscv_zcmop)	\
+      && defined(__riscv_zfa)	\
+      && defined(__riscv_zfh)	\
+      && defined(__riscv_zknd)	\
+      && defined(__riscv_zkne)	\
+      && defined(__riscv_zknh)	\
+      && defined(__riscv_zksed)	\
+      && defined(__riscv_zksh)	\
+      && defined(__riscv_zkt)	\
+      && defined(__riscv_zvbb)	\
+      && defined(__riscv_zvfh)	\
+      && defined(__riscv_zvkt)	\
+      && defined(__riscv_sdtrig)	\
+      && defined(__riscv_sha)		\
+      && defined(__riscv_shlcofideleg)	\
+      && defined(__riscv_smaia)	\
+      && defined(__riscv_smcsrind)	\
+      && defined(__riscv_smdbltrp)	\
+      && defined(__riscv_smmpm)	\
+      && defined(__riscv_smnpm)	\
+      && defined(__riscv_smrnmi)	\
+      && defined(__riscv_smstateen)	\
+      && defined(__riscv_ssaia)	\
+      && defined(__riscv_ssccptr)	\
+      && defined(__riscv_sscofpmf)	\
+      && defined(__riscv_sscounterenw)	\
+      && defined(__riscv_sscsrind)	\
+      && defined(__riscv_ssdbltrp)	\
+      && defined(__riscv_ssnpm)	\
+      && defined(__riscv_sspm)	\
+      && defined(__riscv_ssstrict)	\
+      && defined(__riscv_sstc)		\
+      && defined(__riscv_sstvala)	\
+      && defined(__riscv_sstvecd)	\
+      && defined(__riscv_ssu64xl)	\
+      && defined(__riscv_supm)		\
+      && defined(__riscv_svade)	\
+      && defined(__riscv_svbare)	\
+      && defined(__riscv_svinval)	\
+      && defined(__riscv_svnapot)	\
+      && defined(__riscv_svpbmt))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+  return 0;
+}