[PATCH v2] RISC-V: Remove float vector eqne pattern

We can unify eqne and other comparison operations.

Tested on RV32 and RV64

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
	* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns
	(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
	(*pred_eqne<mode>_scalar): Ditto
	(*pred_eqne<mode>_scalar_narrow): Ditto

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test.

3 files changed, 56 insertions, 92 deletions

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b6f6e4f..596b88c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1420,12 +1420,8 @@ public:
     switch (e.op_info->op)
       {
 	case OP_TYPE_vf: {
-	  if (CODE == EQ || CODE == NE)
-	    return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
-					       e.vector_mode ()));
-	  else
-	    return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
-					       e.vector_mode ()));
+	  return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
+					     e.vector_mode ()));
 	}
 	case OP_TYPE_vv: {
 	  return e.use_compare_insn (CODE,
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index fbcdf96..f8fae65 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7545,92 +7545,6 @@
    (set_attr "mode" "<MODE>")
    (set_attr "spec_restriction" "none,thv,thv,none,none")])
 
-(define_expand "@pred_eqne<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand")
-	     (match_operand 6 "vector_length_operand")
-	     (match_operand 7 "const_int_operand")
-	     (match_operand 8 "const_int_operand")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSF
-	        (match_operand:<VEL> 5 "register_operand"))
-	      (match_operand:V_VLSF 4 "register_operand")])
-	  (match_operand:<VM> 2 "vector_merge_operand")))]
-  "TARGET_VECTOR"
-  {})
-
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
-  [(set (match_operand:<VM> 0 "register_operand"              "=vm")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "register_operand"         "  0")
-	     (match_operand 5 "vector_length_operand"         " rK")
-	     (match_operand 6 "const_int_operand"             "  i")
-	     (match_operand 7 "const_int_operand"             "  i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 2 "equality_operator"
-	     [(vec_duplicate:V_VLSF
-	        (match_operand:<VEL> 4 "register_operand"     "  f"))
-	      (match_operand:V_VLSF 3 "register_operand"      " vr")])
-	  (match_dup 1)))]
-  "TARGET_VECTOR"
-  "vmf%B2.vf\t%0,%3,%4,v0.t"
-  [(set_attr "type" "vfcmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "merge_op_idx" "1")
-   (set_attr "vl_op_idx" "5")
-   (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-   (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vr,   vr,   &vr,   &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"         "   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"             "    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSF
-	        (match_operand:<VEL> 5 "register_operand"     "    f,    f,    f,    f"))
-	      (match_operand:V_VLSF 4 "register_operand"      "   vr,   vr,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0,    vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vmf%B3.vf\t%0,%4,%5%p1"
-  [(set_attr "type" "vfcmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vm,   vr,   vr,  &vr,  &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "    0,vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"         "   rK,   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"             "    i,    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSF
-	        (match_operand:<VEL> 5 "register_operand"     "    f,    f,    f,    f,    f"))
-	      (match_operand:V_VLSF 4 "register_operand"      "   vr,    0,    0,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vmf%B3.vf\t%0,%4,%5%p1"
-  [(set_attr "type" "vfcmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
 ;; -------------------------------------------------------------------------------
 ;; ---- Predicated floating-point merge
 ;; -------------------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c
new file mode 100644
index 0000000..572bcb8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+#define CMP_FLOAT_VF_1(ID, S, OP, IMM)                                         \
+  vbool##S##_t test_float_1_##ID##_##S (vfloat##S##m1_t op1, size_t vl)        \
+  {                                                                            \
+    return __riscv_vmf##OP##_vf_f##S##m1_b##S (op1, IMM, vl);                  \
+  }
+
+CMP_FLOAT_VF_1 (0, 32, eq, 0.0)
+CMP_FLOAT_VF_1 (1, 32, eq, 1.0)
+CMP_FLOAT_VF_1 (2, 32, eq, __builtin_nanf ("123"))
+CMP_FLOAT_VF_1 (3, 32, ne, 0.0)
+CMP_FLOAT_VF_1 (4, 32, ne, 1.0)
+CMP_FLOAT_VF_1 (5, 32, ne, __builtin_nanf ("123"))
+
+CMP_FLOAT_VF_1 (0, 64, eq, 0.0)
+CMP_FLOAT_VF_1 (1, 64, eq, 1.0)
+CMP_FLOAT_VF_1 (2, 64, eq, __builtin_nan ("123"))
+CMP_FLOAT_VF_1 (3, 64, ne, 0.0)
+CMP_FLOAT_VF_1 (4, 64, ne, 1.0)
+CMP_FLOAT_VF_1 (5, 64, ne, __builtin_nan ("123"))
+
+#define CMP_FLOAT_VF_2(ID, S, OP, IMM)                                         \
+  vfloat##S##m1_t test_float_2_##ID##_##S (vfloat##S##m1_t op1,                \
+					   vfloat##S##m1_t op2, size_t vl)     \
+  {                                                                            \
+    vfloat##S##m1_t op3 = __riscv_vfmv_s_f_f##S##m1 (IMM, vl);                 \
+    vbool##S##_t mask1 = __riscv_vmf##OP##_vf_f##S##m1_b##S (op1, IMM, vl);    \
+    vbool##S##_t mask2 = __riscv_vmf##OP##_vv_f##S##m1_b##S (op1, op3, vl);    \
+    vbool##S##_t mask3 = __riscv_vmor (mask1, mask2, vl);                      \
+    return __riscv_vmerge_vvm_f##S##m1_tu (op1, op1, op2, mask3, vl);          \
+  }
+
+CMP_FLOAT_VF_2 (0, 32, eq, 0.0)
+CMP_FLOAT_VF_2 (1, 32, eq, 1.0)
+CMP_FLOAT_VF_2 (2, 32, eq, __builtin_nanf ("123"))
+CMP_FLOAT_VF_2 (3, 32, ne, 0.0)
+CMP_FLOAT_VF_2 (4, 32, ne, 1.0)
+CMP_FLOAT_VF_2 (5, 32, ne, __builtin_nanf ("123"))
+
+CMP_FLOAT_VF_2 (0, 64, eq, 0.0)
+CMP_FLOAT_VF_2 (1, 64, eq, 1.0)
+CMP_FLOAT_VF_2 (2, 64, eq, __builtin_nan ("123"))
+CMP_FLOAT_VF_2 (3, 64, ne, 0.0)
+CMP_FLOAT_VF_2 (4, 64, ne, 1.0)
+CMP_FLOAT_VF_2 (5, 64, ne, __builtin_nan ("123"))
+
+/* { dg-final { scan-assembler-times {vmfeq\.vf} 12 } } */
+/* { dg-final { scan-assembler-times {vmfne\.vf} 12 } } */
+/* { dg-final { scan-assembler-times {vmfeq\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {vmfne\.vv} 6 } } */