c4x.h (PREFERRED_RELOAD_CLASS): Change to restrict the reloading of framepointer + constant to ADDR_REGS class.

2000-01-27 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl>

	* c4x.h (PREFERRED_RELOAD_CLASS): Change to restrict the reloading
	of framepointer + constant to ADDR_REGS class.
	* c4x.md (addqi3, addqi3_noclobber_reload): Update.
	* c4x.c (std_or_reg_operand): New function.
	* c4x-protos.h (std_or_reg_operand): Prototype it.

From-SVN: r31681

5 files changed, 43 insertions, 25 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 91a48d9..4a59cac 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2000-01-27 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl>
+
+	* c4x.h (PREFERRED_RELOAD_CLASS): Change to restrict the reloading
+	of framepointer + constant to ADDR_REGS class.
+	* c4x.md (addqi3, addqi3_noclobber_reload): Update.
+	* c4x.c (std_or_reg_operand): New function.
+	* c4x-protos.h (std_or_reg_operand): Prototype it.
+
 2000-01-29 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl>
 
 	* t-c4x: Change qi,qf,di,df into si,sf,hi,hf to generate same
diff --git a/gcc/config/c4x/c4x-protos.h b/gcc/config/c4x/c4x-protos.h
index dd15fe4..f5ebd16 100644
--- a/gcc/config/c4x/c4x-protos.h
+++ b/gcc/config/c4x/c4x-protos.h
@@ -126,6 +126,8 @@ extern int ext_reg_operand PARAMS ((rtx, enum machine_mode));
 
 extern int std_reg_operand PARAMS ((rtx, enum machine_mode));
 
+extern int std_or_reg_operand PARAMS ((rtx, enum machine_mode));
+
 extern int dst_operand PARAMS ((rtx, enum machine_mode));
 
 extern int src_operand PARAMS ((rtx, enum machine_mode));
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index 294e912..e1071f2 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -2970,6 +2970,18 @@ std_reg_operand (op, mode)
 }
 
 
+/* Standard precision or normal register.  */
+
+int
+std_or_reg_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (reload_in_progress)
+    return std_reg_operand (op, mode);
+  return reg_operand (op, mode);
+}
+
 /* Address register.  */
 
 int
diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h
index 2232300..c450188 100644
--- a/gcc/config/c4x/c4x.h
+++ b/gcc/config/c4x/c4x.h
@@ -815,7 +815,17 @@ enum reg_class
 #define REGNO_OK_FOR_INDEX_P(REGNO) \
      (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
 
-#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
+/* If we have to generate framepointer + constant prefer an ADDR_REGS
+   register. This avoids using EXT_REGS in addqi3_noclobber_reload.  */
+
+#define PREFERRED_RELOAD_CLASS(X, CLASS)			\
+     (GET_CODE (X) == PLUS					\
+      && GET_MODE (X) == Pmode					\
+      && GET_CODE (XEXP ((X), 0)) == REG			\
+      && GET_MODE (XEXP ((X), 0)) == Pmode			\
+      && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM		\
+      && GET_CODE (XEXP ((X), 1)) == CONST_INT			\
+	? ADDR_REGS : (CLASS))
 
 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
 
@@ -2608,6 +2618,7 @@ if (final_sequence != NULL_RTX)		\
   {"ext_low_reg_operand", {REG, SUBREG}},			\
   {"ext_reg_operand", {REG, SUBREG}},				\
   {"std_reg_operand", {REG, SUBREG}},				\
+  {"std_or_reg_operand", {REG, SUBREG}},			\
   {"addr_reg_operand", {REG, SUBREG}},				\
   {"index_reg_operand", {REG, SUBREG}},				\
   {"dp_reg_operand", {REG}},					\
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index bd7e119..98b989a 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -1755,7 +1755,7 @@
 ; so we must emit the pattern that doesn't clobber CC.
 ;
 (define_expand "addqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
+  [(parallel [(set (match_operand:QI 0 "std_or_reg_operand" "")
                    (plus:QI (match_operand:QI 1 "src_operand" "")
                             (match_operand:QI 2 "src_operand" "")))
               (clobber (reg:CC_NOOV 21))])]
@@ -1881,31 +1881,16 @@
 ; (set (mem (reg ar0)) (plus (reg ar3) (const_int 8))).
 ; This is an invalid C4x insn but if we don't provide a pattern
 ; for it, it will be considered to be a move insn for reloading.
-; The nasty bit is that a GENERAL_REGS class register, say r0,
-; may be allocated to reload the PLUS and thus gen_reload will
-; emit an add insn that may clobber CC.
 (define_insn "*addqi3_noclobber_reload"
-  [(set (match_operand:QI 0 "reg_operand" "=a*c,a*c,a*c,!*d,!*d,!*d")
-        (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,%0,rR,rS<>")
-                 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))]
+  [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c")
+        (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
+                 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
   "reload_in_progress"
-  "*
-   if (IS_STD_REG (operands[0]))
-     {
-       if (which_alternative == 0 || which_alternative == 3)
-	 return \"addi\\t%2,%0\";
-       else
-	 return \"addi3\\t%2,%1,%0\";
-     }
-   else
-     {
-       if (which_alternative == 0 || which_alternative == 3)
-	 return \"push\\tst\\n\\taddi\\t%2,%0\\n\\tpop\\tst\";
-       else
-	 return \"push\\tst\\n\\taddi3\\t%2,%1,%0\\n\\tpop\\tst\";
-     }
-   "
-  [(set_attr "type" "binary,binary,binary,multi,multi,multi")])
+  "@
+   addi\\t%2,%0
+   addi3\\t%2,%1,%0
+   addi3\\t%2,%1,%0"
+  [(set_attr "type" "binary,binary,binary")])
 ; Default to int16 data attr.