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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-08-23 10:11:06 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-23 10:13:02 +0800 |
| commit | ea1eb12a38f09e494d5ef072e55653a6463d57eb (patch) | |
| tree | ca36dcc5209333dc3112360d9d9f9ae8c438b7c0 | |
| parent | d18296e844f35c529f338569622b85fc44d68b5f (diff) | |
| download | gcc-ea1eb12a38f09e494d5ef072e55653a6463d57eb.zip gcc-ea1eb12a38f09e494d5ef072e55653a6463d57eb.tar.gz gcc-ea1eb12a38f09e494d5ef072e55653a6463d57eb.tar.bz2 | |
RISC-V: Add attribute to vtype change only vsetvl
This patch is prepare patch for VSETVL PASS.
Commited.
gcc/ChangeLog:
* config/riscv/vector.md: Add attribute.
| -rw-r--r-- | gcc/config/riscv/vector.md | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index e772e79..6ceae25 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1363,7 +1363,11 @@ "TARGET_VECTOR" "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3" [(set_attr "type" "vsetvl") - (set_attr "mode" "SI")]) + (set_attr "mode" "SI") + (set (attr "sew") (symbol_ref "INTVAL (operands[0])")) + (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])")) + (set (attr "ta") (symbol_ref "INTVAL (operands[2])")) + (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))]) ;; vsetvl zero,rs1,vtype instruction. ;; The reason we need this pattern since we should avoid setting X0 register |