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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-29 14:41:00 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-29 14:41:00 +0800 |
| commit | e9fd9efc8d64f944cb480322ee5ed2d0a46db87d (patch) | |
| tree | 2e5261ba778efb52acbb8e6176576718b5fbf51f | |
| parent | ff313e1c74b0360688cdd4a8894486b3941366cf (diff) | |
| download | gcc-e9fd9efc8d64f944cb480322ee5ed2d0a46db87d.zip gcc-e9fd9efc8d64f944cb480322ee5ed2d0a46db87d.tar.gz gcc-e9fd9efc8d64f944cb480322ee5ed2d0a46db87d.tar.bz2 | |
RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974
PR target/109974
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 30 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c | 17 |
2 files changed, 46 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 9847d64..fe55f4c 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2) return false; if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2))) return false; - gcc_assert (insn1->uses ().size () == insn2->uses ().size ()); + /* RTL_SSA uses include REG_NOTE. Consider this following case: + + insn1 RTL: + (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159]) + (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201]) + (reg:DI 14 a4 [276]))) 408 {*umindi3} + (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201]) + (const_int 2 [0x2])) + (nil))) + The RTL_SSA uses of this instruction has 2 uses: + 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice. + 2. (reg:DI 14 a4 [276]) - once. + + insn2 RTL: + (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160]) + (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199]) + (reg:DI 14 a4 [276]))) 408 {*umindi3} + (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) + (const_int 2 [0x2])) + (nil))) + The RTL_SSA uses of this instruction has 3 uses: + 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once + 2. (reg:DI 14 a4 [276]) - once + 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once + + Return false when insn1->uses ().size () != insn2->uses ().size () + */ + if (insn1->uses ().size () != insn2->uses ().size ()) + return false; for (size_t i = 0; i < insn1->uses ().size (); i++) if (insn1->uses ()[i] != insn2->uses ()[i]) return false; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c new file mode 100644 index 0000000..06a8562 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include <stdint-gcc.h> + +void +func (int8_t *__restrict x, int64_t *__restrict y, int n) +{ + for (int i = 0, j = 0; i < n; i++, j +=2 ) + { + x[i + 0] += 1; + y[j + 0] += 1; + y[j + 1] += 2; + } +} + +/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ |