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authorzhongjuzhe <juzhe.zhong@rivai.ai>2022-08-30 09:50:24 +0800
committerKito Cheng <kito.cheng@sifive.com>2022-09-01 09:33:04 +0800
commite9f827d79102001d5f0593f0f9e01ab72b2aec9a (patch)
tree28cbc1de70517cbe09a4b94caebda758aad68c5a
parent542c60c4fb557ec437e3d20634fd59a61d619ac3 (diff)
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RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN
gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Change configuration according to TARGET_MIN_VLEN. * config/riscv/riscv.h (UNITS_PER_FP_REG): Fix comment.
-rw-r--r--gcc/config/riscv/riscv.cc13
-rw-r--r--gcc/config/riscv/riscv.h2
2 files changed, 8 insertions, 7 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4d439e1..5e68fcc 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5219,22 +5219,23 @@ riscv_init_machine_status (void)
static poly_uint16
riscv_convert_vector_bits (void)
{
- /* The runtime invariant is only meaningful when vector is enabled. */
+ /* The runtime invariant is only meaningful when TARGET_VECTOR is enabled. */
if (!TARGET_VECTOR)
return 0;
- if (TARGET_VECTOR_ELEN_64 || TARGET_VECTOR_ELEN_FP_64)
+ if (TARGET_MIN_VLEN > 32)
{
- /* When targetting Zve64* (ELEN = 64) extensions, we should use 64-bit
- chunk size. Runtime invariant: The single indeterminate represent the
+ /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
+ Otherwise we can not include SEW = 64bits.
+ Runtime invariant: The single indeterminate represent the
number of 64-bit chunks in a vector beyond minimum length of 64 bits.
Thus the number of bytes in a vector is 8 + 8 * x1 which is
- riscv_vector_chunks * 8 = poly_int (8, 8). */
+ riscv_vector_chunks * 8 = poly_int (8, 8). */
riscv_bytes_per_vector_chunk = 8;
}
else
{
- /* When targetting Zve32* (ELEN = 32) extensions, we should use 32-bit
+ /* When targetting minimum VLEN = 32, we should use 32-bit
chunk size. Runtime invariant: The single indeterminate represent the
number of 32-bit chunks in a vector beyond minimum length of 32 bits.
Thus the number of bytes in a vector is 4 + 4 * x1 which is
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 1d8139c2..29582f7 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -160,7 +160,7 @@ ASM_MISA_SPEC
/* The `Q' extension is not yet supported. */
#define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
-/* Size per vector register. For zve32*, size = poly (4, 4). Otherwise, size = poly (8, 8). */
+/* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */
#define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
/* The largest type that can be passed in floating-point registers. */