diff options
| author | zhongjuzhe <juzhe.zhong@rivai.ai> | 2022-08-30 14:13:51 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-09-01 09:55:21 +0800 |
| commit | e8089aff3602447cd66ea723802d43cec4e7ec02 (patch) | |
| tree | 9fecf28370e83a361ce3175a6a62fe28005ca061 | |
| parent | 45f1287268200ffd551faca83d5e819b279ade9f (diff) | |
| download | gcc-e8089aff3602447cd66ea723802d43cec4e7ec02.zip gcc-e8089aff3602447cd66ea723802d43cec4e7ec02.tar.gz gcc-e8089aff3602447cd66ea723802d43cec4e7ec02.tar.bz2 | |
RISC-V: Add RVV constraints.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add
"vr" constraint.
(TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint.
(TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint.
(vp): Add poly constraint.
| -rw-r--r-- | gcc/config/riscv/constraints.md | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 2873d53..8997284 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -108,3 +108,23 @@ A constant @code{move_operand}." (and (match_operand 0 "move_operand") (match_test "CONSTANT_P (op)"))) + +;; Vector constraints. + +(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register (if available).") + +(define_register_constraint "vd" "TARGET_VECTOR ? VD_REGS : NO_REGS" + "A vector register except mask register (if available).") + +(define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS" + "A vector mask register (if available).") + +;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov<mode>". +;; VLENB is a run-time constant which represent the vector register length in bytes. +;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register length in bytes. +;; We should only allow the poly equal to BYTES_PER_RISCV_VECTOR. +(define_constraint "vp" + "POLY_INT" + (and (match_code "const_poly_int") + (match_test "known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR)"))) |