diff options
| author | Jakub Jelinek <jakub@redhat.com> | 2019-12-17 10:23:59 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2019-12-17 10:23:59 +0100 |
| commit | e55cdb1455417b139374bf2eee5fce6692b48de7 (patch) | |
| tree | 26d7ac06dd80e596788db424e4585ebf203984bf | |
| parent | da86c5af207cb04869108aa79b2d0117752e291a (diff) | |
| download | gcc-e55cdb1455417b139374bf2eee5fce6692b48de7.zip gcc-e55cdb1455417b139374bf2eee5fce6692b48de7.tar.gz gcc-e55cdb1455417b139374bf2eee5fce6692b48de7.tar.bz2 | |
re PR target/92962 (Documentation: x86 Options - znver2 missing RDPID and WBNOINVD)
PR target/92962
* common/config/i386/i386-common.c (processor_alias_table): Formatting
fixes.
* doc/invoke.texi (bdver3, bdver4, znver1): Add missing closing paren.
(znver2): Likewise. Add RDPID and WBNOINVD, remove spurious comma
before CLWB.
From-SVN: r279455
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/common/config/i386/i386-common.c | 10 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 17 |
3 files changed, 24 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bd1a252..7ab0171 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2019-12-17 Jakub Jelinek <jakub@redhat.com> + + PR target/92962 + * common/config/i386/i386-common.c (processor_alias_table): Formatting + fixes. + * doc/invoke.texi (bdver3, bdver4, znver1): Add missing closing paren. + (znver2): Likewise. Add RDPID and WBNOINVD, remove spurious comma + before CLWB. + 2019-12-17 Hongyu Wang <hongyu.wang@intel.com> PR target/92651 diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index d3e861b..0de0138 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -1617,7 +1617,7 @@ const pta processor_alias_table[] = {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE, - PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR}, + PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"prescott", PROCESSOR_NOCONA, CPU_NONE, @@ -1775,12 +1775,12 @@ const pta processor_alias_table[] = | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID | PTA_WBNOINVD}, {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE}, {"btver2", PROCESSOR_BTVER2, CPU_BTVER2, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1 + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f04e915..5beb023 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -27767,35 +27767,38 @@ instruction set extensions.) CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) + @item bdver2 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) + @item bdver3 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and -64-bit instruction set extensions. +64-bit instruction set extensions.) + @item bdver4 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, -SSE4.2, ABM and 64-bit instruction set extensions. +SSE4.2, ABM and 64-bit instruction set extensions.) @item znver1 AMD Family 17h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit -instruction set extensions. +instruction set extensions.) + @item znver2 AMD Family 17h core based CPUs with x86-64 instruction set support. (This -supersets BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, +supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, -SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit -instruction set extensions.) - +SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID, +WBNOINVD, and 64-bit instruction set extensions.) @item btver1 CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This |