i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole AVX10.1

Based on the feedback we got, we would like to re-alias avx10.x to 512
bit in the future. This leaves the current avx10.1 alias to 256 bit
inconsistent. Since it has been there for GCC 14.1 and GCC 14.2,
we decide to deprecate avx10.1 alias. The current proposal is not
adding it back in the future, but it might change if necessary.

For -mno- options, it is confusing what it is disabling when it comes
to avx10. Since there is barely usage enabling AVX10 with 512 bit
then disabling it, we will only provide -mno-avx10.x options in the
future, disabling the whole AVX10.x. If someone really wants to disable
512 bit after enabling it, -mavx10.x-512 -mno-avx10.x -mavx10.x-256 is
the only way to do that since we also do not want to break the usual
expression on -m- options enabling everything mentioned.

However, for avx10.1, since we deprecated avx10.1, there is no reason
we should have -mno-avx10.1. Thus, we need to keep -mno-avx10.1-[256,512].
To avoid confusion, we will make -mno-avx10.1-512 to disable the
whole AVX10.1 set to match the future -mno-avx10.x.

gcc/ChangeLog:

	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro.
	(OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed.
	(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed.
	(OPTION_MASK_ISA2_AVX10_1_UNSET): New.
	(ix86_handle_option): Adjust AVX10.1 unset macro.
	* common/config/i386/i386-isas.h: Remove avx10.1.
	* config/i386/i386-options.cc
	(ix86_valid_target_attribute_inner_p): Ditto.
	(ix86_option_override_internal): Adjust warning message.
	* config/i386/i386.opt: Remove mavx10.1.
	* doc/extend.texi: Remove avx10.1 and adjust doc.
	* doc/sourcebuild.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10-check.h: Change to avx10.1-256.
	* gcc.target/i386/avx10_1-1.c: Ditto.
	* gcc.target/i386/avx10_1-13.c: Ditto.
	* gcc.target/i386/avx10_1-14.c: Ditto.
	* gcc.target/i386/avx10_1-21.c: Ditto.
	* gcc.target/i386/avx10_1-22.c: Ditto.
	* gcc.target/i386/avx10_1-23.c: Ditto.
	* gcc.target/i386/avx10_1-24.c: Ditto.
	* gcc.target/i386/avx10_1-3.c: Ditto.
	* gcc.target/i386/avx10_1-5.c: Ditto.
	* gcc.target/i386/avx10_1-6.c: Ditto.
	* gcc.target/i386/avx10_1-8.c: Ditto.
	* gcc.target/i386/pr117946.c: Ditto.
	* gcc.target/i386/avx10_1-12.c: Adjust warning message.
	* gcc.target/i386/avx10_1-19.c: Ditto.
	* gcc.target/i386/avx10_1-17.c: Adjust to no-avx10.1-512.

22 files changed, 31 insertions, 46 deletions

diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 52ad1c5..793d684 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -249,7 +249,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
    | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
    | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
-   | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
+   | OPTION_MASK_ISA2_AVX10_1_UNSET)
 #define OPTION_MASK_ISA_AVX512F_UNSET \
   (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
    | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
@@ -325,11 +325,9 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
 #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
-#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
-  (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET \
-   | OPTION_MASK_ISA2_AVX10_2_256_UNSET)
-#define OPTION_MASK_ISA2_AVX10_1_512_UNSET \
-  (OPTION_MASK_ISA2_AVX10_1_512 | OPTION_MASK_ISA2_AVX10_2_512_UNSET)
+#define OPTION_MASK_ISA2_AVX10_1_UNSET \
+  (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512 \
+   | OPTION_MASK_ISA2_AVX10_2_256_UNSET | OPTION_MASK_ISA2_AVX10_2_512_UNSET)
 #define OPTION_MASK_ISA2_AVX10_2_256_UNSET OPTION_MASK_ISA2_AVX10_2_256
 #define OPTION_MASK_ISA2_AVX10_2_512_UNSET \
   (OPTION_MASK_ISA2_AVX10_2_512 | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
@@ -1378,8 +1376,8 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       else
 	{
-	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET;
-	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET;
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
 	  opts->x_ix86_no_avx10_1_explicit = 1;
 	}
       return true;
@@ -1394,8 +1392,8 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       else
 	{
-	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET;
-	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET;
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
 	  opts->x_ix86_no_avx10_1_explicit = 1;
 	}
       return true;
diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 8976b03..52e2dd3 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -183,7 +183,6 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
   ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
   ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
-  ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1")
   ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256")
   ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512")
   ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2_256, P_NONE, "-mavx10.2")
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 7e85334..b9be670 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1134,7 +1134,6 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
     IX86_ATTR_ISA ("apxf", OPT_mapxf),
     IX86_ATTR_ISA ("evex512", OPT_mevex512),
     IX86_ATTR_ISA ("usermsr", OPT_musermsr),
-    IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256),
     IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
     IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
     IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2_256),
@@ -2732,7 +2731,7 @@ ix86_option_override_internal (bool main_args_p,
 	  && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512)
 	      & opts->x_ix86_isa_flags2_explicit))
 	{
-	  warning (0, "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> "
+	  warning (0, "%<-mno-avx10.1-256, -mno-avx10.1-512%> "
 		      "cannot disable AVX512 instructions when "
 		      "%<-mavx512XXX%>");
 	  /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 5c889b7..0ee5c52 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1373,11 +1373,6 @@ Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
 and AVX10.1-512 built-in functions and code generation.
 
-mavx10.1
-Target Alias(mavx10.1-256)
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-and AVX10.1 built-in functions and code generation.
-
 mavx10.2-256
 Target Mask(ISA2_AVX10_2_256) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 065bd8b..8ff850a 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7600,20 +7600,17 @@ Enable/disable the generation of the USER_MSR instructions.
 Enable/disable the generation of the APX features, including
 EGPR, PUSH2POP2, NDD and PPX.
 
-@cindex @code{target("avx10.1")} function attribute, x86
-@item avx10.1
-@itemx no-avx10.1
-Enable/disable the generation of the AVX10.1 instructions.
-
 @cindex @code{target("avx10.1-256")} function attribute, x86
 @item avx10.1-256
 @itemx no-avx10.1-256
-Enable/disable the generation of the AVX10.1 instructions.
+Enable the generation of the AVX10.1 instructions with 256 bit support.
+Disable the generation of the AVX10.1 instructions.
 
 @cindex @code{target("avx10.1-512")} function attribute, x86
 @item avx10.1-512
 @itemx no-avx10.1-512
-Enable/disable the generation of the AVX10.1 512 bit instructions.
+Enable the generation of the AVX10.1 instructions with 512 bit support.
+Disable the generation of the AVX10.1 instructions.
 
 @cindex @code{target("avx10.2")} function attribute, x86
 @item avx10.2
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 797775e..d638125 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2611,11 +2611,8 @@ Target supports compiling @code{avx} instructions.
 @item avx_runtime
 Target supports the execution of @code{avx} instructions.
 
-@item avx10.1
-Target supports the execution of @code{avx10.1} instructions.
-
 @item avx10.1-256
-Target supports the execution of @code{avx10.1} instructions.
+Target supports the execution of @code{avx10.1-256} instructions.
 
 @item avx10.1-512
 Target supports the execution of @code{avx10.1-512} instructions.
diff --git a/gcc/testsuite/gcc.target/i386/avx10-check.h b/gcc/testsuite/gcc.target/i386/avx10-check.h
index 87fa818..cabeeda 100644
--- a/gcc/testsuite/gcc.target/i386/avx10-check.h
+++ b/gcc/testsuite/gcc.target/i386/avx10-check.h
@@ -38,7 +38,7 @@ int
 main ()
 {
   /* Run AVX10 test only if host has ISA support.  */
-  if (__builtin_cpu_supports ("avx10.1")
+  if (__builtin_cpu_supports ("avx10.1-256")
 #ifdef AVX10_2
       && __builtin_cpu_supports ("avx10.2")
 #endif
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
index cfd9662..33ce99e 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
index 61f0e4d..ae1c77b 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-12.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */
-/* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
+/* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
 /* { dg-final { scan-assembler "%zmm" } } */
 
 #include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
index 8a11119..e94ac8e 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-13.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256" } */
 /* { dg-final { scan-assembler "%zmm" } } */
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
index 03222a7..76573e6 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-14.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
@@ -4,7 +4,7 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("avx10.1"))) __m512d
+__attribute__ ((target ("avx10.1-256"))) __m512d
 foo ()
 { /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
   __m512d a, b;
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
index a19230f..09f1252 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-17.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
@@ -4,9 +4,9 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("no-avx10.1"))) __m512d
+__attribute__ ((target ("no-avx10.1-512"))) __m512d
 foo ()
-{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
   __m512d a, b;
   a = a + b;
   return a;
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
index 7aacc15..7445ecf 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-19.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
@@ -6,7 +6,7 @@ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
 __attribute__ ((target ("avx512f"))) __m512d
 foo ()
-{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
   __m512d a, b;
   a = a + b;
   return a;
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
index 27a7265..0a1fcc9 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-21.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mevex512 -Wno-psabi" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mevex512 -Wno-psabi" } */
 /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
index 7962622..cb649dc 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-22.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -Wno-psabi" } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
index 6e8d64d..f31c636 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-23.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
@@ -4,7 +4,7 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("avx10.1"))) __m512d
+__attribute__ ((target ("avx10.1-256"))) __m512d
 foo ()
 { /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
   __m512d a, b;
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
index 2e93f04..1bba0fb 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-24.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 
 typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
index 3be988a..a176f27 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
index 20b78ea..3079cf1 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-5.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-options "-O0 -march=x86-64 -mavx10.1-256 -Wno-psabi" } */
 /* { dg-final { scan-assembler-not ".%zmm" } } */
 
 #include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
index fbc92d5..60dbd05 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-6.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
index 69b6c6a..ec930f7 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-8.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
@@ -1,4 +1,4 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f -mno-evex512" } */
 
 #include "avx10_1-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr117946.c b/gcc/testsuite/gcc.target/i386/pr117946.c
index 7304e01..e7b660b 100644
--- a/gcc/testsuite/gcc.target/i386/pr117946.c
+++ b/gcc/testsuite/gcc.target/i386/pr117946.c
@@ -1,5 +1,5 @@
 /* { dg-do compile  { target { ! ia32 } } } */
-/* { dg-options "-O -favoid-store-forwarding -mavx10.1 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */
+/* { dg-options "-O -favoid-store-forwarding -mavx10.1-256 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */
 typedef __attribute__((__vector_size__ (64))) _Decimal32 V;
 
 void