RISC-V: Fix RVV related testsuite

Use wrapper of riscv_vector.h for RVV related testcases,
more detail see https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603140.html

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/mov-1.c: Use double quotes to
	include riscv_vector.h rather than angle brackets.
	* gcc.target/riscv/rvv/base/mov-10.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-11.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-12.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-13.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-2.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-3.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-4.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-5.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-6.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-7.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-8.c: Ditto.
	* gcc.target/riscv/rvv/base/mov-9.c: Ditto.
	* gcc.target/riscv/rvv/base/vread_csr.c: Ditto.
	* gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
	* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.

16 files changed, 16 insertions, 16 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
index 6a235e3..cfc565b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
index 10aa829..419f19d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
index f8da5bb..1bb159c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
index 5b8ce40..7886886 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov14:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
index 8c630f3..9515e07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 void mov1 (int8_t *in, int8_t *out) 
 { 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
index b9bdd51..301607a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov2:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
index a7a89db..ea69ab2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
index e8cfb4b..50bbd10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
index 5ca232b..680b4f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
index 41fc73b..6348b38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
index d4636e0..c60920a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* This testcase is testing whether RISC-V define REGMODE_NATURAL_SIZE.  */
 void foo (int8_t *in, int8_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
index 9447b05..f2cb244 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
index 6d39e3c..902d65e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* Test tieable of RVV types with same LMUL.  */
 /*
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
index fa643c5..69c9c1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
@@ -2,7 +2,7 @@
 /* { dg-additional-options "-O3" } */
 /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 unsigned long vread_csr_vstart(void) {
   return vread_csr(RVV_VSTART);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
index 661f2c9..60d3b49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
 #include <stddef.h>
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 size_t test_vsetvl_e8mf8_imm0()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
index e23da4b..f9b4e88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
@@ -2,7 +2,7 @@
 /* { dg-additional-options "-O3" } */
 /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 void vwrite_csr_vstart(unsigned long value) {
   vwrite_csr(RVV_VSTART, value);